Apparatus and method for conformal mask manufacturing

ABSTRACT

A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/188,377, filed Jul. 21, 2011, which is a continuation of U.S. patentapplication Ser. No. 11/944,360, filed Nov. 21, 2007, now U.S. Pat. No.7,993,813, which claims priority under 35 U.S.C. §119(e) to U.S.Provisional Application Ser. No. 60/860,619 filed on Nov. 22, 2006,titled “Apparatus And Method For Conformal Mask Manufacturing,” which ishereby expressly incorporated by reference in its entirety.

BACKGROUND

1. Field

The present application relates to semiconductor manufacturing. Morespecifically, the present application relates to methods and apparatusesfor direct write semiconductor manufacturing.

2. Description of the Related Art

Photolithography has been a key patterning step in most integratedcircuit fabrication processes. Resist, a photosensitive organic, is spunon a workpiece, baked, and exposed in a pattern through a reticle,usually by ultraviolet (UV) light. After development and often a secondbake, the surface is left partially covered by an inert organic filmthat resists various treatments to which the workpiece is subjected.Such treatments include material removal by wet chemical etch or bygaseous plasma etch, doping by ion implantation (e.g., broad beamimplantation), and addition of material (e.g., metal lift-off). Thepreparation, exposure, development, clean, care, and stripping of resistcan increase the number of fabrication steps tenfold, requiringexpensive equipment and facilities to establish stable, qualified, andhigh yield fabrication.

Photolithography has been the main lithographic tool for processingpatterns of resist down to 45 nanometers (nm). However, present andfuture microelectronics will require minimum feature sizes below 45 nm.While advances in a number of lithography techniques (e.g., ultraviolet(UV), enhanced ultraviolet (EUV) emersion, maskless emersion, laser,phase-shift, projection ion, and electron beam lithography (EBL)) canenable high-scale production at these dimensions, they are nearing theirtheoretical limits with respect to wavelength, overlay accuracy, and/orcost. Pushed to the limit, the weaknesses of each process presentdifficult problems, and the resulting patterning defects can result insignificant yield loss.

SUMMARY

In certain embodiments, a method for processing comprises providing aworkpiece comprising a layer that is configured to be patterned by aparticle beam and a first transfer layer thereunder, the particle beampatternable layer being thinner than the first transfer layer; andexposing regions of the particle beam patternable layer using acollimated beam of spatially and temporally resolved charged particlesthereby changing said regions, wherein the first transfer layer isconfigured to be selectively processed relative to the particle beampatternable layer using a first process that removes regions of thefirst transfer layer substantially determined by the shape of theexposed regions of the particle beam patternable layer.

In certain embodiments, a method for forming structures comprisesproviding a workpiece comprising a layer that is configured to bepatterned by a collimated beam of spatially and temporally resolvedcharged particles and a first transfer layer thereunder; exposingregions of the particle beam patternable layer to a stream of chargedparticles thereby changing said regions; removing the exposed regions ofthe particle beam patternable layer to reveal regions of the firsttransfer layer having a shape substantially determined by the shape ofthe exposed regions of the particle beam patternable layer; andperforming a first process on the first transfer layer thereby removingregions of the first transfer layer having a shape substantiallydetermined by the shape of the exposed regions of the particle beampatternable layer.

In certain embodiments, a method for processing comprises providing aworkpiece comprising a layer that is configured to be patterned by aparticle beam, a first transfer layer under the patternable layer, and asecond transfer layer under the first transfer layer; and exposingregions of the particle beam patternable layer to a stream of chargedparticles thereby changing said regions, wherein the first transferlayer is configured to be selectively processed relative to the particlebeam patternable layer using a first process that removes regions of thefirst transfer layer substantially determined by the shape of theexposed regions of the particle beam patternable layer, and wherein theselectivity of the first removal process to the first transfer layerrelative to the patternable layer is at least 10 times, and wherein thesecond transfer layer is configured to be selectively processed relativeto the first transfer layer using a second process that removes regionsof the second transfer layer substantially determined by the shape ofthe exposed regions of the particle beam patternable layer.

In certain embodiments, a method for forming structures comprisesproviding a workpiece comprising a layer that is configured to bepatterned by a particle beam, a first transfer layer under the particlebeam patternable layer, and a second transfer layer under the firstlayer, wherein the first transfer layer is configured to be selectivelyprocessed relative to the particle beam patternable layer using a firstprocess that removes regions of the first transfer layer substantiallydetermined by the shape of the exposed regions of the particle beampatternable layer, and wherein the selectivity of the first removalprocess to the first transfer layer relative to the particle beampatternable layer is at least 10 times, wherein the second transferlayer is configured to be selectively processed relative to the firsttransfer layer using a second process that removes regions of the secondtransfer layer substantially determined by the shape of the exposedregions of the particle beam patternable layer, and exposing regions ofthe particle beam patternable layer to a stream of charged particlesthereby changing said regions; removing the exposed regions of theparticle beam patternable layer to reveal regions of the first transferlayer having a shape substantially determined by the shape of theexposed regions of the particle beam patternable layer; performing thefirst removal process on the first transfer layer; and performing thesecond removal process on the second transfer layer.

In certain embodiments, an in-process workpiece comprises a substrate; afirst transfer layer; a second transfer layer between the first transferlayer and the substrate, said second transfer layer comprising organicmaterial; and a patterned layer of oxide, the first transfer layerdisposed between the oxide layer and the second transfer layer, whereinthe first transfer material is configured to be selectively etchedrelative to the oxide layer and relative to the second transfer layer,and wherein the second transfer layer is configured to be selectivelyetched relative to the first transfer layer.

In certain embodiments, a method for processing comprises providing aworkpiece comprising a first transfer layer; and depositing material onregions of the first transfer layer using a particle beam therebyforming on the first transfer layer a layer having a pattern, whereinthe first transfer layer is configured to be selectively processedrelative to the patterned layer using a first process that removesregions of the first transfer layer substantially determined by theshape of the deposited regions of the patterned layer.

For purposes of summarizing the invention and the advantages achievedover the prior art, certain objects and advantages of the invention havebeen described herein above. Of course, it is to be understood that notnecessarily all such objects or advantages may be achieved in accordancewith any particular embodiment of the invention. Thus, for example,those skilled in the art will recognize that the invention may beembodied or carried out in a manner that achieves or optimizes oneadvantage or group of advantages as taught or suggested herein withoutnecessarily achieving other objects or advantages as may be taught orsuggested herein.

All of these embodiments are intended to be within the scope of theinvention herein disclosed. These and other embodiments will becomereadily apparent to those skilled in the art from the following detaileddescription of the preferred embodiments having reference to theattached figures, the invention not being limited to any particularpreferred embodiment(s) disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the inventiondisclosed herein are described below with reference to the drawings ofpreferred embodiments, which are intended to illustrate and not to limitthe invention.

FIG. 1A is a perspective view of an example apparatus for controlledparticle beam manufacturing.

FIG. 1B is a top schematic view of the apparatus of FIG. 1A.

FIG. 2 is a schematic block diagram of an example charged particle beamcolumn, exposure chamber, and control electronics.

FIG. 3A is a schematic block view of an example charged particle column.

FIG. 3B schematically illustrates bunching of charged particles.

FIG. 3C schematically illustrates an example beam buncher.

FIG. 3D schematically illustrates an example beam blanker.

FIG. 4A illustrates an example writing strategy over a period of time.

FIG. 4B is a schematic block diagram of an example workpiece stage andpositional control electronics.

FIGS. 4C and 4D is a schematic block diagram illustrating an examplebeam measurement technique.

FIG. 5 illustrates example groups of charged particles in a digitalbeam.

FIG. 6A depicts a top schematic view of a deflector.

FIG. 6B is a perspective quarter cut-away view of the upper rightquadrant of the deflector of FIG. 6A.

FIG. 7 is a schematic block diagram of another example charge particlecolumn.

FIG. 8 illustrates an example writing strategy.

FIGS. 9A through 9C schematically illustrate cross-sections of aworkpiece at various stages of an example digital beam assisted chemicaletching process.

FIGS. 10A through 10C schematically illustrate cross-sections of aworkpiece at various stages of an example digital beam assisteddeposition process.

FIGS. 11A through 11D schematically illustrate cross-sections of aworkpiece at various stages of an example digital beam implantationprocess.

FIGS. 11E through 11I illustrate example modifications during a digitalbeam modification process.

FIGS. 12A through 12C depict example schematic cross-sections of lightlydoped drain structures processed with a controlled particle beam.

FIGS. 13A and 13B depict an example schematic cross-section of a lateralchannel doping structure processed with a controlled particle beam and adoping concentration profile thereof, respectively.

FIGS. 14A and 14B depict example schematic cross-sections ofheterojunction insulating gate field effect transistor structuresprocessed with a controlled particle beam.

FIG. 15 depicts example schematic cross-sections of gallium arsenidediode structures over time as processed with a controlled particle beam.

FIGS. 16A through 16K depicts example schematic cross-sections ofgallium arsenide microwave monolithic integrated circuit structures overtime as processed with a controlled particle beam.

FIG. 17 depict an example schematic cross-section of a heterojunctionbipolar transistor structure processed with a controlled particle beam.

FIG. 18 depicts example schematic cross-sections of a semiconductorstructure over time as processed with a controlled particle beam.

FIG. 19A depicts an example schematic top view of a radiation hardnessstructure processed with a controlled particle beam.

FIG. 19B is a schematic cross-sectional view of the radiation hardnessstructure of FIG. 19A taken along line 19B-19B.

FIG. 20 depicts an exploded cross-sectional schematic view of anobjective lens assembly.

FIGS. 21A through 21G schematically depict beam writing strategies.

FIGS. 22A through 22D schematically depict an example embodiment of amethod for forming a conformal mask. FIG. 22D shows the completed “darkfield” conformal mask.

FIGS. 23A through 23F schematically depict another example embodiment ofa method for forming a conformal mask. FIG. 22F shows the completed“light field” conformal mask.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although certain preferred embodiments and examples are disclosed below,it will be understood by those in the art that the invention extendsbeyond the specifically disclosed embodiments and/or uses of theinvention and obvious modifications and equivalents thereof. Thus, it isintended that the scope of the invention herein disclosed should not belimited by the particular disclosed embodiments described below.

Smaller device geometries can be achieved by direct writing with a beamof charged particles. Focused ion beam (FIB) systems generally do nothave sufficient ion exposure to support high throughput manufacturing.Furthermore, only relatively low speed deflection is available usingexisting ion optics/deflection electronics methodologies, preventingefficient direct write of layers patterned for semiconductor devices. Assuch, FIB has been limited to mask (e.g., reticle) and semiconductorrepair. As FIB technology progressed, it supported the ability tosimultaneously deposit, etch, and implant patterns directly onworkpieces without the use of resist. Problems remained, however,including low energy systems with little-to-no wafer writing software,no metrology systems, and minimal beam current densities and deflectionspeeds necessary to support the lithography on a high manufacturingscale. Modifications and improvements to FIB systems in accordance withembodiments described herein can achieve suitable manufacturingthroughput in both resist processing and resistless fabrication ofsemiconductor workpieces and other media (e.g., photomask, compact disk(CD), digital video disk (DVD), high definition DVD (HD DVD), Blue-Ray,etc.).

The physical properties of a beam of charged particles traveling alongan axis with a distribution transverse to the axis can be modified toprovide a high speed, digital (or “pulsed”) distributed writing beam.Various methods can be used to create a wave of temporally and spatiallydefined high-density charged particle anti-nodes and low density (or nodensity) nodes, traveling in a longitudinal path of acceleratedparticles (herein referred to as a “digitized beam”). For example, abeam buncher can be used to create localized groups (or “flashes” or“packets”) of the charged particles. These groups of charged particlescan contain one or more charged particles. The digital beam is thenpassed through a deflector, whereupon variations in voltage cause thegroups of charged particles to change position relative to the directionof propagation. Changes in voltage can be timed in phase with theparticle anti-nodes, thereby yielding efficient deflection. The presenceof a sharp edge of the node effectively provides fast beam blanking fordirect write. Applying the digitized beam to the surface of a workpieceallows resistless patterned processing, including deposition, etching,and/or implantation of material to the surface of the workpiece and/orhigh resolution resist exposure.

FIG. 1A is a perspective view of an example apparatus 100 in accordancewith certain embodiments disclosed herein. FIG. 1B is a top schematicview of the apparatus 100 of FIG. 1A. The apparatus 100 comprises anexposure chamber 102, a load lock chamber 104, a transport module 106,and a plurality of processing chambers 108. Although not illustrated, itwill be understood that the apparatus 100 comprises a gas manifoldsystem and an automated process controller, described in more detailbelow.

The load lock chamber 104 may house workpieces 101 that are not beingprocessed, for example, before and/or after processing in the apparatus100. In certain embodiments, the load lock chamber 104 is configured toachieve vacuum such that an automated material handling system (AMHS)110 of the transport module 106 in communication with the load lockchamber 104 may insert and/or remove workpieces 101 without having to bepumped down to or up from vacuum between each transfer. In certainembodiments, the loadlock chamber 104 is configured to accept a frontopening unified pod (FOUP).

The transport module 106 is configured to move workpieces 101 within theapparatus 100. The transport module 106 comprises an AMHS 110 configuredto manipulate at least one workpiece 101. A suitable AMHS 110 can bechosen based on the design of the exposure chamber 102, the loadlockchamber 104, the transport module 106, and/or the process chambers 108.In certain embodiments, the AMHS 110 comprises a plurality of transportarms such that workpieces 101 may be manipulated simultaneously (or inparallel).

In some embodiments, the transport module 106 includes a workpieceprealigner, such that the workpieces 101 removed by the transport arm110 and subsequently placed into the exposure chamber 102 or a processchamber 108 are in an orientation that is ready for processing in theexposure chamber 102 or a process chamber 108. For example, theprealigner may use charge-coupled device (CCD) or other imaging devicesto locate a flat, notch, or other identifying feature of the workpiece101. In some embodiments, the prealigner is configured to determineoverlay parameters of alignment features on the workpiece 101. Theoverlay parameters may comprise x and y offset, rotation, etc.

Depending on the type and size of the workpiece 101, a variety of vacuumand handling systems can be used in the apparatus 100. A system capableof processing a variety of workpieces preferably uses a high speedworkpiece handling system. Workpiece-into-vacuum throughput can beincreased by aligning the workpiece under vacuum on the workpiece stageinstead of outside the vacuum system. A standard workpiece holder (e.g.,a wafer magazine) can be pumped to high vacuum within a few minutes.Alignment of the workpiece 101 under vacuum may increase wafer intovacuum throughput.

In some embodiments, the transport module 106 comprises one or moreprocessing substations, for example comprise one or more buffer zones tohold workpieces 101 between processing steps, a particle contaminationdetector, a temperature quenching station, and/or a metrology station.The metrology station may be selected from any tool appropriate for thattype of workpiece, including, but not limited to, an energy dispersiveanalyzer (EDS), a wavelength dispersive analyze (WDS), a secondary ionmass spectrometer (SIMS), a scanning electron microscope (SEM), atwo-dimensional laser scanning imager, a three-dimensional imaging laserradar (LADAR), a thermal imager, a millimeter wave imager, a workpieceimager, and a camera.

The exposure chamber 102 is configured to expose a workpiece 101 to adigital beam of charged particles. As shown in FIG. 2, the exposurechamber 102 comprises a beam column 200, illustrated in more detail inFIG. 3A. The beam column 200 comprises a charged particle source 202 forgenerating a stream of charged particles. Although systems and methodsare described in certain embodiments herein with reference to ions, itwill be understood that some systems and methods may utilize chargedparticles comprising electrons and positrons. Charged particles mayinclude one or more species of positively and negatively charged ions,as well as singly, doubly, triply, etc. charged ions. In someembodiments, the charged particle source 202 is adapted to generate aplurality of ion species. In some embodiments, the charged particlesource 202 is adapted to provide a current of 1,000 amperes/cm² (A/cm²)focused to a 10 nm spot as measured at the target.

Liquid metal ion source (LMIS) technology enables the formation of highcurrent density charged particle beams. An example technique to create aLMIS is a heated reservoir of liquid metal from which a needle protrudesdownward. The metal flows down the needle by capillary action. Anelectric field from an extraction electrode pulls the liquid at the tipof the needle into a sharp cusp (a “Taylor Cone”) from which ions areemitted. The point source is very bright (e.g., about 10⁹A/steradian/cm²), and, with suitable optics, permits the beam diameterto be as small as 2 nm. A variety of alloys provides several ion speciescommon for semiconductor fabrication.

Accelerating and focusing a distributed energy of ions can introducechromatic aberrations resulting in a loss of current density efficiencyof the ion optic system. The ion beam energy distribution can bemeasured as the beam full-width-half-max (FWHM) and can be distributedas much as 12%. Improving the current density efficiency and resolvinglong and short term stability issues can make LMIS performance adequatefor a semiconductor processing tool. One aspect of various embodimentsof the present invention is the realization that beams of chargedparticles are composed of a distribution of high and low energy tails,which can be advantageously grouped.

At least two mechanisms can contribute to the broadening of the energydistributions: first, effects related to the formation of the ions; andsecond, space charge forces after ion formation. Ion emissions from aLMIS source are formed either by direct field desorption of an ion atthe emitter tip or by field ionization of desorbed atoms at somedistance from the emitter tip. Ions generated close to the tip surfacecan exchange charge with neutral atoms further downstream, forcing azero energy ion at that point. Since the electric field in the emitterarea is high (e.g., between about 20 and 50 Volts/nm), ions formed atdifferent distances from the emitter can have different energies. Spacecharge effects broaden the energy distribution of the beam, particularlyat low velocities. Therefore, the column 200 preferably is configured toaccelerate the ions to full energy directly after formation. The use oflow-mass species may aid in ion acceleration when the use of suchspecies is appropriate.

Space charge effects are also aggravated by higher currents. For theLMIS source, the width of the energy distribution is preferablyproportional to the current to the ⅔ power. As such, practicalapplication of traditional LMIS sources to lithography show behaviorsimilar to electron beams.

A limitation on the maximum current density achievable with LMIS-basedsystems results from the energy distribution of the ion beam that iscaused by the achromatic aberration in the upper ion optical system.However, the use of a beam digitizer 206 downstream of the chargedparticle source 202 that is configured to adjust the longitudinalspacing between charged particles so as to create temporally andspatially resolved groups of the charged particles along the axis ofpropagation can effectively slow faster moving particles and can speedslower moving particles to obtain a uniform velocity, and thus a uniformenergy distribution (accelerating voltage) within each group of thedigital beam, thereby reducing the effect of the charged particle sourcechromatic aberration, as illustrated in FIG. 3B.

Similar to the drift of an electron beam, a LMIS Taylor cone emissionunpredictably drifts, typically in a figure-8 pattern over about a onehour period. Undetected, this drift can cause pattern placement errors.Source lifetime and current stability are barriers to the practicalapplication for production throughput processing tools using traditionalLMIS sources. Further improvements at the charged particle source 202can improve the stability and lifetime, thereby reducing frequent sourcereplacement. The broadening of the energy distribution associated withion formation can be reduced or minimized by operating the LMIS at lowtemperature, thereby decreasing the neutral atom density in theproximity of the tip. The energy distribution can also be reduced orminimized by choosing a low vapor pressure species, for example byselecting a doubly ionized species that has a low charge exchangecross-section and that is formed at the surface of the tip, known tohave a narrow energy distribution, and by using a species that has theadditional benefit of a small virtual source. It will be appreciatedthat other techniques can also be used.

In certain embodiments, extended lifetime of the charged particle source202 may be achieved by conditioning the source driving parameters priorto operation. As such, the incorporation of an automated conditioningroutine can contribute to the extended life and stability of the chargedparticle source 202. Additionally, a continuous flow strategy, such asimpregnated electrode-type needles with hardened tips, can furtherextend the life span of the charged particle source 202. Second ordereffects of improved life span can include emission current and positionstability improvement. Source emission position stability can besuccessfully corrected by using an error feedback from occasional beamregistrations and adjustment to source servomotors. Although increasedion beam current density is preferred, the column 200 in the exposurechamber 102 need not increase the beam current density.

Other charged particle sources 202 may also be used with the embodimentsdisclosed herein. For example and without limitation, the chargedparticle source 202 may comprise a plasma ion source (PIS), a volumeplasma ion source (VPIS), a gas field ionization source (GFIS), a carbonnanotube field emitter, a free electron laser and a target, a pulsedlaser ablation ion source, a magnetically confined plasma anode source(MAP), and a thermal field emission (TFE) electron source.

The stream of charged particles emanating from the charged particlesource 202 is collimated and directed along a axis by a collimator 204.A variety of collimators 204 comprising a combination of opticalelements are appropriate for use in the column 200. For example, andwithout limitation, the collimator 204 may comprise two or more lensesor a lens and a reflective optic. The collimator 204 may furthercomprise an aperture configured to shape the charged particle beam. Incertain embodiments, the collimator is adapted to direct the chargedparticle stream at accelerating potentials between about 5 and 30 kiloelectron volts (keV). In certain embodiments, the exposure chamber 102is adapted to direct the charged particle stream at acceleratingpotentials between about 5 and 500 keV. In some embodiments, a voltageof the collimator 204 is additive to additional voltages, for exampleapplied by a lower column exit aperture.

In embodiments in which the charged particle source 202 is adapted togenerate a plurality of ion species, individual ion species can beselected for specific processing applications by filtering the chargedparticle stream with a particle filter (e.g., a spectrometer filter).For example, a mass separator can be configured to deflect selected ionspecies into a mass separator aperture plate. The mass separator ispreferably disposed between the collimator 204 and the beam digitizer206. In some embodiments, the mass separator comprises a reflectiveoptic. In some embodiments, the mass separator comprises an ExB lens. Insome embodiments, the mass separator comprises a Wein filter.

The beam digitizer 206 is configured to create a digital beam comprisingdiscrete groups of at least one charged particle by adjusting thelongitudinal spacing between charged particles along the axis ofpropagation. In certain embodiments, the beam digitizer 206 isconfigured to create groups comprising between about 1 and 7,000,000charged particles, between about 1 and 100,000 charged particles,between about 1 and 10,000 charged particles, or between about 1 and50,000 charged particles. In some embodiments, the beam digitizer 206 isconfigured to create longitudinal spacing D between groups of chargedparticles of less than about 10 m of beam travel, less than about 1 m ofbeam travel, less than about 10 cm of beam travel, less than about 10 mmof beam travel, less than about 1 mm of beam travel, less than about 500μm of beam travel, less than about 300 μm of beam travel, less thanabout 100 μm of beam travel, less than about 10 μm of beam travel, lessthan about 100 nm of beam travel, less than about 10 nm of beam travel,or less than about 1 nm of beam travel between the groups of chargedparticles. In some embodiments, the beam digitizer 206 is configured tocreate longitudinal spacing between the groups of charged particles ofbetween about 1 nm and 10 m of beam travel, between about 1 nm and 1 mof beam travel, between about 1 nm and 10 cm of beam travel, betweenabout 1 nm and 10 mm of beam travel, between about 1 nm and 1 mm of beamtravel, between about 1 nm and 500 μm of beam travel, between about 1 nmand 300 μm of beam travel, between about 1 nm and 100 μm of beam travel,between about 1 nm and 10 μm of beam travel, between about 1 nm and 100nm of beam travel or between about 1 nm and 10 nm of beam travel. Thelongitudinal spacing between the groups of charged particles may besubstantially equal, unequal, periodic, harmonic, etc.

In certain embodiments, the beam digitizer 206 comprises a beam buncher.In a radio frequency (RF) beam buncher, a stream of charged particlespass through a buncher gap where they are acted upon by an alternatingpotential, RF or multiple modulating potential wave forms, beat wave,harmonic, variable, or a combination thereof. Velocity modulationcompresses the charged particles together so that they form spatiallyand temporally resolved discrete groups of charged particles. In certainembodiments, the frequency and the buncher gap length are configured tomatch a mean velocity of the groups of charged particles. The appliedpotential modulates the longitudinal velocity of each charged particleas they pass through the buncher gap so that some charged particles(e.g., charged particles with a lower velocity than the mean velocity)are accelerated while other charged particles (e.g., charged particleswith a higher velocity than the mean velocity) are decelerated (e.g., asdepicted in FIG. 3B). The gap length of the buncher gap, the magnitudeand frequency of the applied potential, and the time of flight (TOF) ofthe charged particles through the column 200 determine the finalcharacteristics of the digital beam and the groups of charged particlesat the surface of the workpiece 101.

FIG. 3C schematically depicts a stream of charged particles travelingthrough a beam buncher. A potential can be applied across the electrodes302, 304 of the beam buncher that are separated by buncher gap G. Ifunaltered thereafter, the charged particles begin to form groups whoselength L and separation (spacing) D depend on how far the chargedparticles have traveled after passing through the beam buncher. In someembodiments, the beam buncher is configured to compress the chargedparticles into groups during travel. In some embodiments, the beambuncher is configured to apply an electric field to longitudinallycompress the groups of charged particles. The charged particles arepreferably fully compressed in the longitudinal direction when theyreach the workpiece 101 (e.g., as depicted in FIG. 3C). The energyapplied by the buncher can be determined by the difference between theinitial energy of the stream of charged particles and the final energyof the temporally and spatially resolved groups of the chargedparticles.

In certain embodiments, the beam buncher comprises a plurality ofbuncher electrodes and therefore a plurality of buncher gaps. Thepotential can be selectively applied across two of the electrodes inorder to change the characteristics of the digital beam. For example, apotential can be applied across electrodes with a buncher gap G of 1 μmto create nodes with a lower charged particle density and applied acrosselectrodes with a buncher gap G of 3 cm to create nodes with a highercharged particle density.

The relationships between beam buncher input parameters such as beamenergy and buncher current, frequency, and gap length and beam buncheroutput characteristics such as separation D, length L, and density arewell known. The beam buncher is preferably operated to provide a givennumber of charged particles per group. First, the buncher gap,frequency, and beam energy can be held constant while the current isadjusted. Second, the beam energy and buncher current can be heldconstant while the buncher gap and frequency are adjusted. Otheroperation configurations are also possible.

In some embodiments, the beam buncher comprises a helical coil that ismodulated with a current frequency, resulting in a magnetic field. Thelongitudinal spacing (“gap”) between turns of the coil, the magnitudeand frequency of the applied current, and the time of flight (TOF) ofthe charged particles through the column 200 determine the finalcharacteristics of the digital beam at the surface of the workpiece 101.In certain embodiments, the frequency and longitudinal spacing betweenturns of the coil are configured to match a mean velocity of the digitalbeam.

Bunching charged particles allows write strategy optimization with dosevariations at the charged particle level by varying the beam buncherfrequency, amplitude, and duty cycle, which in turn varies the chargedparticle density, as described above. The beam buncher parameters aretherefore preferably adjusted according to the write strategy.

In certain embodiments, the beam digitizer 206 comprises a beam blanker(e.g., a beam blanker that can operate at speeds sufficient to create adigital beam). For example and without limitation, the high speedblanker may comprise an aperture plate configured to absorb the chargedparticle beam at certain intervals. The aperture plate is initiallypositioned such that the stream flows through the aperture in theaperture plate proximate to an interior edge of the aperture plate. Anelectrode is configured to deflect the stream into the aperture plate,which intercepts the flow of particles to create a temporally andspatially resolved digital beam. FIG. 3D schematically depicts a streamof charged particles traveling through a high speed blanker. An apertureplate 316 is positioned proximate to the stream of charged particles.The electrodes 312, 314 are configured to apply a potential to thecharged particle stream to create temporally and spatially resolvedgroups of charged particles of the digital beam. If unalteredthereafter, the charged particles continue to travel with length L andseparation D regardless of how far the charged particles have traveledafter passing through the high speed blanker.

Other embodiments of the beam digitizer 206 are also possible. In someembodiments, the beam digitizer 206 is configured to modulate an on/offstate of the charged particle source 202. In some embodiments, the beamdigitizer 206 is configured to modulate a position of the chargedparticle source 202 longitudinal to the axis so as to displace thegroups of charged particles.

In some embodiments, the beam digitizer 206 is configured to applyelectromagnetic radiation, for example with a frequency of between about1 megahertz (MHz) and 100 gigahertz (GHz) or between about 1 MHz and 25GHz. In such an embodiment, the beam digitizer 206 can be configured tomodulate, for example, the amplitude of the electromagnetic radiation,the frequency of the electromagnetic radiation, combinations thereof,and the like. In some embodiments, the beam digitizer 206 is configuredto apply a beat wave to a plasma comprising the charged particles. Insome embodiments, the beam digitizer 206 is configured to apply spacecharges to wake fields. In such embodiments, the beam digitizer 206 canbe configured to resonantly absorb the space charges. In someembodiments, the beam digitizer 206 is configured to blank the beamthrough an absorption aperture. In some embodiments, the beam digitizer206 is configured to apply a pulsed incident neutralizing beam to thecharged particle source 202. In some embodiments, the beam digitizer 206is configured to apply a pulsed laser beam to the charged particlesource 202.

In certain embodiments, components described herein are advantageouslycombined. In an embodiment, the column 200 comprises a beam blankerdownstream of the collimator 204 and a beam buncher downstream of thebeam blanker. A digital beam coming from the beam blanker and into thebeam buncher can be used to further temporally and spatially resolve theindividual groups in the digital beam. In another embodiment, the column200 comprises a beam buncher downstream of the collimator 204 and a beamblanker downstream of the beam buncher. Other configurations are alsopossible.

The column 200 further comprises a deflector 210 downstream of the beamdigitizer 206. The deflector 210 comprises a series of deflection stages(e.g., electrode stages, magnetic stages) disposed longitudinally alongthe axis of the digital beam. The deflector 210 deflects individualgroups of charged particles in the digital beam. As used herein, thephrase “minor field deflection” refers to the deflection of anindividual group of charged particles by the deflector 210. In someembodiments, the deflector 210 is configured to deflect the groups inthe digital beam substantially perpendicularly to the axis ofpropagation. In certain embodiments, the deflector comprises betweenabout 1 and 1,000 or four deflection stages. In certain embodiments, thedeflector comprises at least one, two, three, or four deflection stages.In some embodiments, each deflection stage comprises two or moreelectrodes. In some embodiments, one or more deflection stage comprisesfour electrodes. Other quantities of deflection stages and electrodesare also possible.

In certain embodiments, an average or mean velocity of the groups ofcharged particles in a digital beam is between about 1×10⁴ meters/second(m/s) and 3×10⁸ m/s. In some embodiments, application of potentials byeach of the deflection electrode stages is adapted to be synchronizedwith the mean velocity of the groups of charged particles passingthrough the deflector. For example, a deflection electrode stage may beadapted to apply a voltage only when a group of charged particles ispassing through the deflector in general and through that particulardeflection electrode stage in particular. In some embodiments,application potentials by each of the deflection electrode stages isadapted to be harmonically synchronized with a mean velocity of thegroups of charged particles passing through the deflector. For example,each deflection electrode stage in at least a portion of the deflectormay be adapted to apply a voltage only when a particular group ofcharged particles is passing through the deflector in general andthrough that particular deflection electrode stage in particular. Insome embodiments, application of potentials by each of the deflectionelectrode stages is adapted to be randomly synchronized with a meanvelocity of the groups of charged particles passing through thedeflector. As used herein, the phrase randomly synchronized is to begiven its broadest possible meaning including, but not limited to,synchronization of application of voltage by the deflection electrodestages to groups of charged particles with random spacing orsynchronization of application of voltage by random deflection electrodestages to groups of charged particles with random or other spacing.

In certain embodiments, electrodes of the deflection stage apply asubstantially equal voltage potential as each group of charged particlesof the digital beam passes. The amount of deflection of each group ofcharged particles depends on the number of electrodes activatedsequentially. In some embodiments, variable potentials are applied toeach deflection electrode stage as each group of charged particlespasses. For example, the first deflection electrode stage has thesmallest voltage with subsequent electrodes have progressively morevoltage, resulting in a linear deflection as electrodes are activated.The converse is also possible, where the first deflection electrodestage has the largest voltage with subsequent electrodes havingprogressively less voltage. The number of deflection electrode stagesactivated defines the amount of deflection of each group of chargedparticles of the digital beam. The signal timing and nominal voltagesapplied to the deflector can be calibrated for individual deflectionelectrode stages and even individual electrodes within each deflectionelectrode stage. Triggering an applied voltage of individual deflectionelectrode stages can be delayed if needed to match the incidence of toeach group of charged particles of the digital beam (“phase-matching”),for example due to changes in charged particle velocity, species, andmass, deflection stage position, pattern resolution, pattern fielderrors, errors within an objective deflection field, process specificcompensation and write strategies, combinations thereof, and the like.In certain embodiments, a field perimeter of the deflection electrodestages is defined as the minor deflection field of less then 4 mm, lessthan 2 mm, less than 1 mm, or less than 100 μm displacement in x or yfrom the center of the axis of propagation.

In certain embodiments, the potentials of each of the deflectionelectrode stages are adapted to partially displace the groups of chargedparticles towards an intended trajectory. Each group is partiallydeflected 1/Nth of an intended deflection distance by each of a number Nof deflection electrode stages. In certain embodiments, the firstdeflection electrode stage, or any single deflection electrode stage, isadapted to substantially fully displace one or more (e.g., all) groupsof charged particles towards an intended trajectory, and the otherdeflection electrode stages are used to fine tune the deflection of thegroups. Other combinations are also possible.

In some embodiments, for example the harmonically synchronized deflectordescribed above, at least a portion of the deflector comprises N sets ofdeflection electrode stages, each set of deflection electrode stagecomprising N deflection electrodes, in which every Nth deflectionelectrode stage is configured to displace a particular group of chargedparticles towards an intended trajectory. If at least a portion of thedeflector comprises two sets of deflection electrode stages, every otherdeflection electrode stage in the sets of deflection electrode stagesmay be configured to displace a particular group of charged particlestowards an intended trajectory. If at least a portion of the deflectorcomprises three sets of deflection electrode stages, every thirddeflection electrode stage in the sets of deflection electrode stagesmay be configured to displace a particular group of charged particlestowards an intended trajectory. Other variations and configurations arepossible.

FIG. 6A depicts a top schematic view of a deflector 210 comprising atleast one electrode in each deflection electrode stage. The digital beamcomprising charged particles is configured to flow through the centeraperture of the deflector 602. The sets of electrodes 604, 606 and 608,610 may be positively or negatively charged such groups of chargedparticles are deflected perpendicularly to the longitudinal axis of thedeflector and the path. Preferably, the electrodes on opposing sides,for instance, electrodes 604 and 606, are oppositely charged. FIG. 6B isa perspective quarter cut-away view of the upper right quadrant of thedeflector 210. The electrodes 606 are separated in this embodiment by aninsulator 612. Examples of insulator materials include Al₂O₃, SiO₂,SiN_(x), SiO_(x)N_(y), combinations thereof, and the like. It will beunderstood that rather than a single deflector comprising a plurality ofdeflection electrode stages, the deflector 210 may comprise a series ofdeflectors, each comprising one or more deflection electrode stages. Forexample, a deflector 210 may comprise three sets of deflectors. Asillustrated in FIG. 6B, the groups of charged particles are deflected byeach deflection electrode stage as they travel along the path. Otherdeflector and electrode configurations are possible.

In certain embodiments, the deflector 210 is configured to arrange thegroups of charged particles into a three-dimensional timespace (an“adaptable virtual digital stencil”). In certain embodiments, thedeflector 210 is adapted to create a laterally distributed pattern ofthe groups of charged particles. In some embodiments, the deflector 210further comprises a deflector lens adapted to demagnify the pattern orthe virtual stencil. The deflector lens may comprise an electrostaticlens, an electromagnetic lens, a reflective lens, a combinationreflective and refractive lens, a combination reflective and deflectivelens, a combination deflective and refractive lens, combinations of thesame, and the like. FIG. 7 is a schematic block diagram of a column 200in which the groups of charged particles coming out of the deflector 210are arranged in a virtual digital stencil 702, each group of chargedparticles having undergone a minor field deflection. The objective lensassembly 212 is configured to deflect the virtual stencil with a majorfield deflection. The combination of minor field deflection, major fielddeflection, and movement of the workpiece 101 can be used to expose apattern of charged particles on the workpiece 101.

In certain embodiments, a phase of the groups of charged particles ofthe digital beam longitudinal to the axis is configured to besubstantially equal, single harmonic, multiple harmonic, random,combinations thereof, and the like. The spacing between the deflectionstages may be adapted to be synchronized and to be in phase with thegroups of charged particles. In some embodiments, longitudinal positionsof the deflection electrode stages are adjustable. In some embodiments,the deflector 210 comprises a digital feedback system, for example toadjust the spacing between the deflection electrode stages. Piezos, etc.may be used to position the electrodes or deflection stages.

In some embodiments, the column 200 further comprises an objective lensassembly 212 disposed between the deflector 210 and the workpiece stage214. The objective 212 may comprise a lens, a mirror, a reflectiveoptic, a combination reflective optic and refractive lens, a combinationreflective optic and deflection electrodes, a combination deflectionelectrode and refractive lens, combinations of the same, and the like.In some embodiments, the objective lens assembly 212 comprises adetractive lens assembly or a deflector electrode assembly configured todemagnify, focus, and/or deflect the groups of charged particles or theadaptable virtual digital stencil. For example, in certain embodimentsand without limitation, groups of charged particles having a diameter(or “spot size”) of about 200 nm are reduced 10 times to a diameter ofabout 20 nm. The objective lens assembly 212 may also be adapted todemagnify the groups or the stencil by 100 times or 1,000 times. Inembodiments in which the objective lens assembly 212 is configured todeflect a virtual digital stencil, the deflection may be called a “majorfield” deflection. In some embodiments, a field perimeter of theobjective lens assembly 212 is defined as the major deflection field ofless then 10 mm, less than 5 mm, less than 1 mm, or less than 100 μmdisplacement in x or y from the center of the axis of propagation. Incertain embodiments, the exit aperture comprises an exit aperture.

Referring again to FIG. 2, the exposure chamber 102 comprises aworkpiece stage 214 downstream of the lower objective lens assembly 212.The workpiece stage 214 is configured to hold the workpiece 101.Preferably, the workpiece stage 214 comprises an interferometric stage,wherein the relative position of the stage is measured using opticalinterference. The workpiece stage 214 may be thermally controlled toreduce magnification errors in the workpiece, which can lead to overlayerrors. The workpiece stage is preferably configured to continuouslymove while a workpiece 101 is exposed to the groups of chargedparticles. For example, the workpiece stage 214 may be configured tomove continuously over a dimension of 25 centimeters over a period of 1second during exposing. For another example, the workpiece stage may beconfigured to move without stopping for more than 5 nanoseconds per 0.5seconds during exposing. The ability to continuously expose while movingthe workpiece stage 214 without stopping can yield increase efficiencyand throughput.

In certain embodiments, the workpiece stage 214 comprises aninterferometer configured to determine the location of the workpiecestage 214 in a horizontal plane. The relative x/y position of the stagecan be measured using optical interference. Other methods are alsopossible, for example the workpiece stage may comprise a registrationmark, grid, or feature detectable by a secondary ion mass spectrometer(SIMS), backscattered electronics, or faraday cup disposed below theregistration grid. The registration mark is preferably included in anassembly that can be moved parallel to the column 200 in order tooptimize a working height of the registration mark to the workpiece,thereby reducing column calibration and registration errors. The digitalbeam may periodically or randomly be directed towards the registrationmark to check the alignment of the column. The registration mark mayalso be used to calibrate the column 200 before, after, and/or duringexposing a workpiece.

In some embodiments, the chamber 102 further comprises a height controlsystem that measures the height of the workpiece stage 214 and/or aregistration mark. The height control system can include, for example, alaser and a plurality of detectors configured to receive light emittedfrom the laser and reflected by the workpiece, the workpiece stage 214,and/or a surface that moves with the workpiece. The height controlsystem can compensate for variation in the measured height of theworkpiece stage by adjusting an elevation of the stage, for example byusing electrostatic clamps, piezoelectric devices, etc. In someembodiments, the height control system is configured to compensate forheight variations of less than 1 μm. Electrostatic clamping may be usedto secure the workpiece to the workpiece stage 214 and to ensureadequate thermal contact and flatness of the workpiece.

Full motion writing (FMW) can eliminate the workpiece stage motionoverhead time while exposing a workpiece. In FMW, the deflector 210system is updated in real time to track the motion of the workpiecestage 214, thereby allowing the system to write patterns while theworkpiece stage is in motion. Such a process preferably uses a highspeed optical controller (e.g., laser) to track the position of theworkpiece stage 214. For example, circuitry on the controller canconvert Doppler-shifted laser deflection measurements into laser pulsesthat can be stored in a stage position register. Interferometry, laserdeflection measurements, or other optical techniques can be used totrack the position of the workpiece. Therefore, the throughput oflithography systems can be improved by reducing or eliminatingnonexposure time during stage repositioning and settling sequences.

While exposing a workpiece, each deflection field center is defined by awindow of opportunity (WOO). While the workpiece stage is in motion anda deflection field passes over an unwritten WOO, a stage controllersignals a deflection controller to initiate exposure. The workpiece isexposed while the undeflected beam center passes through the WOO. Withinthe WOO, the deflection system can deflect to the outer limit of thefield. During this time, the deflection system is updated by theworkpiece stage position register of the actual location of theworkpiece stage.

The workpiece stage can allow real time deflection correction. Bychanging the WOO size or frame size, or by smoothing the frame-by framepattern data, the system can be dynamically optimized for continuouswriting. A typical frame/WOO density is depicted in FIG. 4A.

The workpiece stage may be configured to provide suitable velocityperformance, for example at 100 centimeters per second. The workpiecestage may be configured to rotate a workpiece during exposure at up toabout 40,000 rotations per minute (rpm). For example, the workpiecestage may have as little inertia as possible, and a compatible workpiecestage motor design can be provided. The use of vacuum compatible airbearing rails and linear motor drives can provide adequate decoupling ofvibration sources. As additional examples, the workpiece stage motorscan be placed in the vacuum system, light weight materials can be usedfor the workpiece stage, and the workpiece can be aligned on the stage,thereby eliminating the workpiece cassette and cassette clampinghardware. Additionally, the first three derivatives of stage position(velocity, acceleration, and jerk) can be limited and damped byelectronic hardware to properly control the motion of the workpiecestage. FIG. 4B is a schematic diagram of an example workpiece stage andcontrol electronics.

The exposure chamber 102 may be in communication with controlelectronics, for example system support electronics 220 including waferhandler control, vacuum control, suspension control, temperaturecontrol, pressure control, etc. and column support electronics 230including a source control module, digitizer control, deflector control,lens control, wafer height sensor, video processor, stage control, and adynamic corrector (e.g., for real time column aberration correction).The column support electronics 230 may be in communication with dataprocess electronics 240, for example a workstation.

An example application of the systems described herein is to perform insitu workpiece processing or resist exposure by directly writing on theworkpiece. Preferably, accurate registration of optics to the targetworkpiece is achieved, but tool induced shift (TIS) and workpieceinduced shift (WIS) errors may be introduced due to temperature effects,workpiece processing effects, and optical distortions. An examplesolution is to measure an initial pattern (e.g., one or more alignmentmarks) on the workpiece is and to use the measurement data to accuratelyplace a newly patterned image onto the workpiece, for example byadjusting the exposure parameters.

A registration sensor preferably can automatically detect and recognizea variety of registration and alignment mark patterns, materials, andprofiles without impacting the quality of exposure throughput. Examplesto achieve such a sensor include, but are not limited to, using a highresolution, high speed registration system with existing hardware,determine the limitation and flexibility of the registration strategy(e.g., by mapping the workpiece with die-to-die registration) and theincorporating a temperature conditioning stage, and introducing a highspeed moiré (grating) interferometer system for die-to-die registration,combinations thereof, and the like. Other approaches are also possible.

A high resolution, high speed registration system can employ existinghardware and can be similar to existing electron beam registration, buta plurality of imaging modes can be used. Scanning the surface of anobject (e.g., a registration or alignment mark) with a digital beamproduces secondary electron emission, secondary ion emission, and ionsputtering. A bi-axial or cylindrical microchannel plate can be used todetect both secondary electrons (e.g., by biasing above the voltage ofthe target) and the secondary ions (e.g., by biasing below the voltageof the target). Other configurations are also possible. An image can becreated by measuring a signal yield of the secondary ions and secondaryelectrons at each point where the beam impacts the target. Variations inthe yield indicate changes in surface topology or composition of theworkpiece. The position resolution of this signal is a product of themeasured beam spot size and deflection pixel size during registrationand is augmented by statistical metrology. Sputtered ions providegreater mark recognition ability because such ions can be collected andmass analyzed secondary ion mass spectroscopy (SIMS). SIMS registrationtechniques are well developed and can be used both for mark detectionand for process development diagnostics. An atomic map with the spatialresolution of the beam spot size can provide excellent precision formark detection.

To optimize registration, a product summation of the detector videosignal with a computer generated image of the registration or alignmentmark can be used to enhance or recover an otherwise unrecognizabletarget signal from high-noise background. This can be performed byautomatically correlating the video gain and bias offset for an initialsignal enhancement. Once the tone is properly adjusted, the signal canbe correlated with a computer generated (CAD) image of the registrationor alignment mark to provide an enhanced image of the mark. Othersignals are detectable from digital beam mark interaction. Signals suchas those from secondary electrons and backscatter electrons may be usedfor this process. Additionally, signals from secondary electrons andbackscatter electron may be employed differentially to improve detectionlimits (e.g., signal to noise ratios). For example, the final detectionsignal may be the difference between SIMS and other signals. The speedof registration may be limited by the quality of the registrationelectronics, but incorporating modern electronics (e.g., digital signalprocessing (DSP)) may reduce the registration time by orders ofmagnitude without burdening registration resolution.

Another consideration in the quality and speed of registration is theconfiguration used to register to the workpiece prior to exposing.Depending on the pre-conditioned and in-process temperature stability ofthe workpiece, several strategies are available to compensate fordistortions and throughput issues. Workpiece mapping generally registersa single die, providing reduced or minimum overhead to the systemthroughput but no correction for pattern distortion caused bytemperature instability during exposing. Die-to-die registrationperformed immediately prior to die exposure, for example to minimizetemperature distortion effects, generally uses four registrations perdie per level. Such a technique eliminates the ability to write in aserpentine mode, drastically limiting the throughput of the system bymemory load overhead time. However, performing registration on aplurality of dies at one time can maintain the ability to write in aserpentine mode within a field comprising the plurality of dies, therebyallowing increased or maximum throughput while reducing or minimizingpattern distortion.

Overlay accuracy becomes increasingly important as device geometriesshrink. For a digital beam tool, the direct exposure of multi-levelpatterns on a single workpiece for manufacturing of integrated circuitsdesirably includes accurate intra-layer registration. An exampleworkpiece alignment technique has three features: adequate signalgeneration from the surface impact of the digital beam; a detectionalgorithm for processing the detected signal; and an alignment featurefabrication technique.

The impact of a charged particle onto the workpiece can create mediasuch as secondary electrons, backscattered electrons, photons, andsecondary ions, each having certain advantages in detection efficiency.However, selection of a particular media for registration purposesdepends on the charged particle species, the charged particle energy,and the current density of the beam. A signal detector may be optimizedfor a given media. For example, an electron-photomultiplier is generallyappropriate for secondary electrons, a solid state diode is generallyappropriate for backscattered electrons, and secondary ion massdetectors are generally appropriate for photons and secondary ions.

A digital signal processor processes information from the signaldetector in order to determine the location of the alignment mark. Atraditional method of detection includes a one-dimensional line scanwith the digital beam. As the digital beam transitions by deflectionacross the alignment mark, the detected video signal is modulated.Modulation occurs because differences in the alignment mark and thecontour of the workpiece. Actual alignment mark location can bedetermined by processing the distribution of the modulated signal via adigital signal processing module. Another detection method includes anX/Y scanning mode of the digital beam to acquire a video image of thealignment mark. To achieve accurate edge detection, digital signalprocessing algorithms are applied. Improved detection of the alignmentfeature edge is accomplished through a two-dimensional imaging methodthat averages several frames of video data and determines the actuallocation of the alignment mark by gray scale signal processing.

Preferably, alignment marks are formed over the entire working area ofthe workpiece in the form of equally spaced two-dimensional grids. Oneconstruction method is the formation of a raised multi-layeredsemiconductor structure consisting of layers of silicon, silicon dioxide(SiO₂), and polysilicon, with an alignment mark formed on thepolysilicon layer of the wafer. In another construction method, analignment mark is etched into the surface of a silicon wafer and a layerof a heavy metal (e.g., tantalum or tungsten) is deposited into thetrench. The alignment mark containing the heavy metal exhibit a highlevel of backscatter relative to a silicon substrate, thereby providingcontour details for low energy backscatter ion detection. Selection ofan appropriate alignment feature construction method depends on thesignal media and the signal detector, dictated by process steps.

A minimum of three alignment marks are preferred in order to accuratelyidentify translation, rotation, and magnification errors. The measurederrors are fed back to the workpiece stage control system forcorrection, thereby reducing workpiece and tool induced shift errors.The processing of global alignment marks may permit faster and moreaccurate detection of localized alignment marks by removing grosserrors. The alignment process can be repeated whenever the workpiece isinserted into the exposure chamber, whenever the workpiece is removedfrom the apparatus, between significant process steps, etc. Othertechniques can also be used.

Patterning tools transfer large quantities of microelectronic circuitpattern data in a format that can be manipulated (e.g., converted fromdigital to analog) within small periods of time (e.g., nanoseconds). Thedata is typically in a format for very large scale integration (VLSI)computer aided design (CAD), as described below. This data is used, forexample, to control the deflection by the deflector 210, the deflectorlens, the objective lens 212, and/or movement of the workpiece stage 214and can be adjusted to address aberrations in the optics. Chargedparticle exposure chambers may have imperfections (e.g., aberration,deflection errors), for example due to manufacturing or installationimperfections and the physical constraints of the optics. As an example,if a system is installed with a slight rotation relative to theworkpiece stage 214, beam deflections will be rotated relative to themotion of the workpiece stage 214. More complex errors may also bepresent; for example, an attempt to trace the outline of a large squarewith the beam may produce a pincushion or barrel shaped pattern. Themagnitude of these effects is proportional to the magnitude ofdeflection of the digital beam, which can limit the size of thedeflection field and can create nonlinear distortions in system writingquality. High resolution writing using a digital beam is thereforepreferably able to augment transformed pattern data to compensate fordeflection field distortion, wafer distorted pattern placement errors,stage position, etc.

Additionally, processing errors may be introduced. Pattern distortion ordeflection distortion can result from several factors when exposing aworkpiece with a digital beam. For example, thermal fluctuations in theexposure chamber 102 or in a workpiece 101 can cause magnificationerrors. For another example, securely clamping the workpiece 101 to theworkpiece stage 214 can also cause rotational errors or can inducestresses resulting in pattern sheering. For yet another example,unrecoverable nonlinear pattern distortions can result from subsequentprocessing such as rapid thermal annealing. For still another example,manufacturing or installation of the optics may be imperfect (e.g., witha slight rotation relative to the workpiece stage) and the optics havecertain physical constraints. More complex errors may be introduced bycertain processes, for example and without limitation, tracing a largesquare with the digital beam may result in a pincushion or barrel shapedpattern. The magnitude of the errors may be proportional to themagnitude of the beam deflection such that they can limit the size ofthe deflection field and can create nonlinear distortions in systemwriting quality. The adaptable virtual digital stencil is in softcode atany given point in time. As such, the stencil is temporally andspatially adaptable to correct in real time for nonlinear patternoffset, gain, rotation, and corrections within the minor field, whilebeing deflected in the major field. These corrections can be performedwithin features, die, or to the entire workpiece.

Digital beam lithography systems preferably can perform pattern and beamcorrections to compensate for processing-induced errors on the workpieceand optical errors (e.g., coma distortion, astigmatism, image puredistortion, chromatic aberration, spherical aberration, field curvature,etc.). Such corrections can improve writing quality and enhance systemthroughput.

Pattern and deflection distortion problems can be corrected byincorporating data manipulation bias electronics (hardware and software)into the system. For example, process control software can use metrologymeasurements to correct the deflection of the digital beam. Suchmetrology measurements preferably are made prior to exposing theworkpiece. The quality of the digital beam may initially be optimized toprovide improved or optimum measurements from subsequent metrology. Insome embodiments (e.g., as depicted by FIG. 4C), a knife-edged micromeshgrid is placed over a diode detector, which is scanned by the digitalbeam. The second derivative of the beam current with respect to the scanposition provides a high resolution beam profile (e.g., as depicted byFIG. 4D). Optimization (e.g., automated optimization) of the beamprofile with the optics control system allows focusing of the beam.

Once the digital beam has been optimized at small or minimum deflectionangles, the system can correct the digital beam profile within a largerusable deflection field by moving the workpiece stage 214 to a pluralityof positions within the outer limits of the distorted deflection field.The digital beam is then deflected to the position where the grid isscanned for beam optimization. The sequence is repeated over an extendedsize of the deflection field. Beam optimization data can then becorrelated with an interferometer or other position monitoring system ofthe workpiece stage 214. In certain embodiments, the linear contributionof the error is stored as an argument, while the nonlinear error isstored as pure memory. Beam distortions that depend on the position of aminor field within a major field can also be correlated. Within theminor field, use of the grid to calibrate deflection distortions can beperformed without moving the workpiece stage by major field deflectionof the adaptable virtual digital stencil to fit the scans on the grid.As a result, automated optimization or improvement of the beam profilecan be performed within an extended deflection system, thereby allowingimproved writing quality and throughput performance.

A final measurement can be made prior to exposing portions (e.g.,individual dies) of the workpiece 101 because the workpiece 101 may berotated or distorted as a result of temperature or stress effects causedby processing. If a pattern is being written on a workpiece 101 thatalready contains previous pattern levels, the new level can be adjustedto overlay on the previous levels, for example by registering to threeor four corners of the die and then applying a magnification orrotational correction within each die. For example, the calibrationsoftware may automatically measure features on the edges of each dieprior to exposure and use the measurements to correct for any patterndisplacement, magnification, or rotation caused while aligning,processing, or handling the workpiece.

As described above, the exposure chamber 102 can be operated byproviding integrated circuit (IC) design data, for example in the formof CAD schematics, to generate and expose the pattern on the workpiece.Users of the apparatus 100 input a desired pattern to be written, alongany specific alignment configurations and/or processing parameters. Oncethe design for a device (e.g., an integrated circuit) is developed,multiple pattern layers of the design can be laid out to cover theworkpiece as desired (e.g., to cover the entire workpiece). A completeexposure data preparation (EDP) package with a user interface can beused to convert raw designs (e.g., in CAD or graphic data system(GDSII)) to a format usable by the exposure chamber 102 (e.g., exposureready format (ERF)). Prior to loading pattern data onto the system,several format changes, such as compressing and merging similar patternfeatures and reducing overlapping routines, can be made to increase ormaximize throughput of the exposure chamber. Once the pattern data hasbeen compressed to a reduced or minimum size, a field partition routinecan define the major and minor deflection fields of the pattern data anduse a smoothing routine to normalize the density in each data frame.Normalization reduces stage jerking when writing repetitious adjacentmultiple density patterns. After registration as described above, thepattern is laid out on the workpiece, using the registration data tocalibrate the intended beam pattern to the actual workpiece pattern andto apply any compensation to improve overlay accuracy.

In various embodiments, for example pattern data in GDSII, OASIS, orother suitable formats is input into the system. The input data is thenfractured into subfields and identified as to whether they are to be“written” or “non-written.” The mapping of the written subfields is sentto a data path module for rasterization (e.g., conversion to a bitmap).Throughput improvement is achieved by moving the workpiece stage anddeflecting the beam from one written subfield to a non-adjacent writtensubfield without exposing non-written subfields. No time is spentprocessing non-written subfields without pattern data.

Various deflection technologies can be used to expose a workpiece tocharged particles. Raster scan is a scanning mode in which the beammoves back and forth over the entire workpiece; the beam is turned onover designated areas and is turned off until the next designated area.Vector scan is a scanning mode in which the digital beam scans onlyselected areas where pattern is to be placed; after scanning of theselected area is completed, the beam is turned off and moved to selectedarea to be scanned. Hybrid vector-raster technology utilizes a vectorapproach for major field deflection between data pattern subfields anduses a raster scan technology to deflect a Gaussian or shaped digitalbeam within the subfield. Throughput improvement can result from onlymoving the workpiece stage to positions that receive exposure. Anotherform of vector-raster includes a vector deflection in the major field, avector deflection between pattern features within the minor field, and araster image of the feature within the minor field. The vectorcapability of a vector-raster system can provide higher throughputversus a pure raster scan system, and the raster capability of thevector-raster system permits good pattern fidelity and high current witha small dwell time.

As described above, in certain preferred embodiments, minor fielddeflection of the digital beam is accomplished through a deflector,which is possible because that the longitudinal spatial and temporalspacing of the groups of charged particles permits the individualdeflection of each group. In certain embodiments, the voltage applied toeach deflection electrode stage is timed to match the velocity of eachgroup of charged particles.

Spacing between groups of charged particles can effectively provideblanking. In particular, such blanking between groups effectively usesthe full flux of a continuous or nearly continuous charged particlestream. The temporal spacing between groups allows for deflection errorcorrection (error correction signal summing can compensate for stagedisposition, deflection aberrations, optical aberrations, and write modeprocess adjustments). Throughput improvement can be achieved bymaximizing the time that the digital beam exposes the workpiece.

In certain preferred embodiments, the digital beam is capable ofperforming a plurality of pattern exposure strategies. Such strategiesmay be designed to modify exposure dose, species, pattern quality, beamenergy per group of charged particles, beam energy for sets of groups,and beam energy for an adaptable virtual digital stencil. The apparatusmay also be capable of discretely modifying exposure dose, species,pattern quality, beam energy per group of charged particles, beam energyfor sets of groups, and beam energy for an adaptable virtual digitalstencil within a particular writing strategy to optimize that particularwriting strategy for a particular process.

In an embodiment of a writing strategy, the beam is scanned in rasterfashion across the entire area of the workpiece. In certain embodiments,the spot size of the beam is greater than the grid spacing in the raster(e.g., as depicted by FIG. 21A). In certain embodiments, the spot sizeof the beam is substantially equal to the grid spacing in the raster(e.g., as depicted by FIG. 21B). That is, the pattern is vector scannedin the major field, vector scanned in the minor field, and rasterscanned in a single pass within the feature to be exposed. Featureprocessing with a digital beam can leverage the per pixel dose variationto improve feature edge quality when performing etch, implant, anddeposition. In some embodiments, a digital beam spot size to pixel ratiogreater than one can average placement of the groups of chargedparticles and can reduce exposure process errors. A large digital beamspot size to pixel ratio improves line edge roughness and allows ahigher dose deposition due to cumulative dosing from overlapping beams.This process can also be performed with or without resist.

In another embodiment of a writing strategy, alternating row and columnexposure is performed with a large spot size and small pixel size ratio.Exposing alternating pixels with a digital beam produces a pixelexposure width half as wide as the selected feature, thereby increasingthe feature critical dimension over target value in both axes (e.g., asdepicted in FIG. 21C). That is, the pattern is vector scanned in themajor field, vector scanned in the minor field, and raster scanned inalternating pixels in both x and y directions with a single pass withinthe feature to be exposed. Throughput is increased by effectivelyreducing the number of charged particles per flash, but at the cost ofcritical dimension control. There are advantages to using this writemode for a digital beam, such as the ability to apply per pixel dosevariation or multiple species exposure to improve device performance,feature edge quality, and throughput when performing resistless etch,implant, and deposition processes. The throughput improvement can bedramatic since system throughput increases as the square of theeffective writing grid. This process can be performed with or withoutresist.

Yet another embodiment of a writing strategy divides pixel spacedmatrices (or “composites”) and overlays exposure of a combination ofcomposites interleaved in a series of passes, with each pass offset fromother passes in both the x and y directions by a fraction of the writingaddress. That is, the pattern is vector scanned in the major field,vector scanned in the minor field, and raster scanned in a series ofpasses that interleave the pixels within the feature to be exposed. Thebeam size can be set 25-100% larger than pixel size in order to averageout the flashes and to reduce the number of charged particles per group(e.g., as depicted in FIG. 21D). A larger beam spot size versus pixelsize helps reduce line edge roughness by averaging systematic errors toallow a higher dose deposition (e.g., as depicted in FIG. 21E). Thereare advantages to using this write mode for a digital beam, such as theability to apply per pixel dose variation to improve feature edgequality when performing direct etch, implant, and deposition processes,thereby improving feature edge quality. This process can also beperformed with or without resist. The feature quality is improved, butmultiple passes are achieved with little or no effect on throughput.

Yet another embodiment of a writing strategy leverages a sampling matrixhaving an array of cells of a predetermined input address size. Eachpass produces a writing grid defined by the distance between beamplacements in a single pass. That is, the pattern is vector scanned inthe major field, vector scanned in the minor field, and raster scannedin a series of passes offset in the x and y directions to createmultiple offset composite feature patterns that interleave the pixelswithin the feature to be exposed. The composite of all passes forms theeffective exposure grid (e.g., as depicted in FIG. 21F). The dose of thebeam can also be freely varied within the operating envelope of thesystem. There are advantages to using this write mode for a digitalbeam, such as the ability to apply per pixel dose variation to improvefeature edge quality when performing resistless etch, implant, anddeposition processes, thereby improving feature edge quality. Thisprocess can also be performed with or without resist with a pixel rategreater than about 400 MHz. A good balance between feature quality andthroughput can thereby be achieved. The dose of the beam can also bevaried within the process-defined operating envelope of the system(e.g., as depicted in FIG. 21G). This can be performed with a number oftechniques including modulating the duty cycle of a beam buncher.Multiple levels of pixel intensity are provided from 0% to 100% beamintensity. Pixels of partial intensity are used along the edge of afeature so as to locate the edge between the lines of a Cartesian rasterscan grid. The dose modulation can be assigned by the user via thepattern data file. There are advantages to using this write mode fordigital beam processing, such as the ability to apply per pixel dosevariation to improve feature edge quality when performing resistlessetch, implant, and deposition processes, thereby improving feature edgequality. This process can also be performed with or without resist. Agood balance between feature quality and throughput can thereby beachieved.

FIG. 8 illustrates an example vector-raster write strategy using adigital beam. The workpiece is divided into square pixels 1 through 44.The beam generally writes in a serpentine motion across the workpiece,from 1 to 4, then from 5 to 12, then from 13 to 22, etc. Each pixel isdivided into stripes, and each stripe is divided into fields, which aredivided into subfields. The beam generally writes in a serpentine motionacross each stripe, field, and subfield as well. Within each subfield,the beam is able to write only where written features exist. Like vectorscanning, the digital beam only scans selected areas, but the beam doesnot need to be turned off to be moved to another area, at least the timethe beam is turned off is reduced as the dead space between the groupsof charged particles can be used for that purpose.

As device geometries decrease, patterning with accurate overlay ispreferably at least one order of magnitude smaller than the minimum orcritical dimension. Workpiece processing and handling may induce patternerrors across the workpiece that contribute to placement errors,especially as geometries fall below 0.25 microns. However, serialpatterning equipment (e.g., exposure chambers with a digital beam) hasthe flexibility to correct for these errors by registration and patterndata augmentation. A fully automated metrology program that commands thedigital beam to align itself, perform deflection/workpiece positioningcalibration, and recognize and correct for wafer pattern distortion caneliminate not only pattern defects at the most recent level, but forother pattern errors, as well.

As previously discussed, beam measurement and laser interferometersystems have accuracies to within a few angstroms. Making use of thesemeasurements, system calibration software can collect the deflectiongain, linearity, offset, and rotation for both the major and minordeflection fields. The deflection is calibrated to the laserinterferometer system, providing a well-behaved deflection motion andprofile of the digital beam within the deflection field. Linear andnonlinear errors of the digital beam profile with respect to the beamdeflection can also be measured and corrected. Because each die isregistered prior to exposure, temperature compensation can be performedby adding corrections to the pattern software and exposing that die in acorrected state, which allows the system to reduce or eliminate patterndistortions caused by annealing, vacuum radiation drain and evaporation,and improper conditioning.

The flexibility of electronic data preparation (EDP) software allowsalterations of the pattern to accommodate processing variability.Pattern editing, tone reversal, and feature biasing provide increasedflexibility to the user of the apparatus 100. In addition, featurebordering, dose by size, and dose by type can improve digital beamassisted chemical etching (DBACE) and digital beam nucleation deposition(DBND) at small geometries.

Preferably, a data manipulation bias system corrects for pattern anddeflection distortion, for example by augmenting pattern data applyingcorrected data to the optics control system. The data manipulator systemapplies final pattern data biasing prior to optics control, andtherefore may include very fast electronics (e.g., the fastestelectronics in the system). This system sums pattern data correction,deflection distortion correction, and workpiece stage motion correctionto the front end of the optics control system. Digital to analogconverters at the front end of the optics control system convert thedigital signals from the data manipulator. Once amplified, these analogsignals drive the column 200.

Overlay accuracy can limit sub-micron lithography. For example,traditional lithography systems cannot correct for nonlinear patterndistortions caused by wafer processing, which is exacerbated byincreased workpiece sizes and reduced device geometries. However,certain digital beam systems described herein can advantageously correctfor such errors because the pattern is not fixed on a reticle, but canchange during exposing. The adaptable virtual digital stencil is insoftcode at any given point in time. It is therefore temporally andspatially adaptable to correct in real time for nonlinear patternoffset, gain, rotation, and corrections within the minor field, whilebeing deflected in the major field. These corrections can be performedwithin features, die, or to the entire wafer.

A method of processing a workpiece 101 in the exposure chamber 102comprises exposing the workpiece 101 to a digital beam of chargedparticles. In certain embodiments, exposing the workpiece 101 comprisesforming a stream of charged particles, collimating and propagating thesteam along an axis, digitizing the stream into a digital beamcomprising groups (or packets or flashes) comprising at least onecharged particle, deflecting the groups of charged particles using aseries of deflection electrode stages disposed longitudinally along theaxis, demagnifying the pattern, and focusing the demagnified pattern ofgroups of charged particles onto the workpiece 101. The dosage ofexposure is preferably less than about 1×10¹⁷ charged particles/cm². Asdescribed above, digitizing the beam may comprise, for example, beambunching, high speed blanking, combinations thereof, and the like.

In some embodiments, deflecting the groups of charged particlescomprises selectively applying voltages across the deflection electrodesat each deflection electrode stage. Selectively applying the voltagesmay comprise applying a large voltage with a first deflection electrodestage and applying smaller voltages with other deflection electrodestages. Selectively applying the voltages may also comprise applying asmall voltage with a first deflection electrode stage and applyinglarger voltages with other deflection electrode stages. Selectivelyapplying voltages may also comprise applying approximately equalvoltages at each deflection electrode stage. Demagnification of thegroups of charged particles preferably produces packet diameters of lessthan about 200 nm, less than about 50 nm, less than about 10 nm, lessthan about 5 nm, or less than about 1 nm. The workpiece stage may movecontinuously during the exposing process. For example, the workpiecestage may move continuously over a dimension of about 100 cm over a timeperiod of 1 second. For another example, the workpiece stage may movewithout stopping for more than 5 nanoseconds per 0.5 seconds.

FIG. 5 illustrates a plurality of groups of charged particles 502, 504.In some embodiments, deflection of a group of charged particles occursduring a dead zone 512 at the workpiece such that no exposing occursduring the deflection. The rise time 509 of saturated beam pulses can beused for blank and unblank edges. In some embodiments, the geometry ofthe groups of charged particles are Gaussian in x and y dimensionsperpendicular in time, as well as Gaussian in velocity to, the axis ofpropagation. In some embodiments (e.g., as depicted in FIG. 5), thegroups of charged particles 502, 504 have a trapezoidal cross-sectionalong the longitudinal axis. In FIG. 5, two groups of charged particles502 and 504 are depicted. Each digital beam has a density distributionrise time 506 and a fall time 508. The time between no charged particlesand the peak density of charged particles is the quick pulse rise time509. The time in which each group 502, 504 has a peak density of chargedparticles is the digital flash time 510. The time between the fullconcentration of charged particles and no charged particles is the quickfall time 511. The time in which there are no charged particles is thedead zone 512 (the anti-node region). The time between the last instanceof a full concentration of charged particles in a first group, forexample the group 502, and the initial concentration of chargedparticles in a subsequent group, for example the group 504, is thedeflection time 514. The time between the first concentration of chargedparticles in a first group, for example the group 502, and the initialconcentration of charged particles for a second subsequent group, forexample the group 504, is the flash duty cycle (or “flash spot rate”)516 and is used for feature-to-feature deflection time within the minorfield. In some embodiments, however, blanking can occur over multipleduty cycles. A blanker may be used.

Referring again to FIGS. 1A and 1B, the apparatus 100 may furthercomprise at least one dedicated process chamber 108. Additional processchambers can optionally be used for advanced processing. The processchambers 108 may comprise any variety of workpiece processing equipment.For example, and without limitation, the processing chambers 108 maycomprise etch, deposition (e.g., oxidation, nucleation, etc.), rapidthermal anneal (RTA), combinations of the same, and the like. Someprocess chambers 108 may be configured to process a workpiece 101 thathas been exposed in the exposure chamber 102, while other processchambers 108 can be configured to process a workpiece 101 before orafter processing in another process chamber 108, before processing inthe exposure chamber 108, etc. In certain embodiments, a process chamber108 does not substantively change the workpiece 101. For example, aprocess chamber 108 may comprise a calibration or metrology tool. Incertain embodiments, the apparatus 100 comprises a plurality ofprocessing chambers 108 such that a workpiece 101 may be transformedfrom a bare substrate to a substantially finished product. Preferably,workpiece 101 can be fully processed without being removed from theapparatus 100. In certain embodiments, the duration from startingsubstrate to substantially finished product is less than one week, morepreferably less than two days, or even more preferably less than oneday, or more preferably yet in less than one hour.

In an example embodiment, two process chambers 108 are dedicated tonucleation and oxidation deposition, a third process chamber 108 isdedicated to rapid thermal annealing, and a fourth process chamber 108is dedicated to chemically-assisted digital beam etching (CADBE).Although one process chamber 108 may be adapted to perform all suchprocesses, dedication allows, for example, the use robust materials toavoid corrosion in the CADBE chamber.

Automated processing software can be used to monitor and analyze allaspects of the system's performance, to perform automation control ofall functional operations, and to optimize each process performed by thesystem. The software can perform a data gathering routine on all sensorsof the system and organize the results into operational and performancerelated reports addressing the status of the system. The software canalso prepare a processing report for each workpiece processed throughthe system including the targeted process compared to the actualprocess, which can be used to determine fault analysis and processboundaries. Feedback of the process parameters into an automated controlloop (e.g., a knowledge based routine) allows high leverage indeveloping processes. The software may incorporate data gathered fromone or more metrology processes to enhance such process development, forexample to monitor and adjust etching rates, deposition thicknesses, andcontamination. The software can preferably operate all system functions,including process sequences, process parameters for each sequence, etc.,although pattern exposure may be controlled by a pattern generationsystem. The software can produce interlocks based on the processsequences and can provide full automation and optimization of theprocesses. Other configurations are possible. User control andadjustment is also used in certain embodiments.

Etching is a process for the manufacture of semiconductor circuits. Highleverage microelectronic integrated circuits generally utilize highresolution etching of materials to within a critical dimension andlocation. The ability to etch metals, semiconductors, and dielectricswith precise control over feature depth, uniformity, anisotropy, andreproducibility is desirable for many applications. Standard processingtechniques typically utilize a resist-related patterning step followedby a wet or dry chemical etch to perform material removal.

Resist patterning limits the quality of the etch process profile, size,depth, and uniformity. Milling, or etching after exposure by a focusedion beam, provides high resolution removal of material without the useof resist. However, high dose and low sensitivity cause slow speed ofthe equipment, and milling has not been commercially successful.Chemically assisted processes (e.g., chemically assisted ion beametching (CAIBE) and reactive ion etching (RIE)) were introduced toenhance milling, but they could not be incorporated into FIB equipmentbecause the gas reacted with several components within the exposurechamber. In contrast, as described herein, low dose procedures incombination with concentrated charged particles in groups compatiblewith resistless processing provides quality patterns and highthroughput.

In certain embodiments, etch, implant, and deposition of the workpiececan be performed within the exposure chamber 102. Multiple activation byexposure to a digital beam and a process gas can dramatically improvethe efficiency of all three processes. A digital beam specificallydesigned for a particular process in terms of energy, species, andcurrent, which is possible because the digital beam parameters areadjustable, can impact and decompose a portion of the process gasmolecules. The decomposed molecules strike surface atoms of theworkpiece to sputter or implant new atoms into the workpiece, or todeposit new atoms on the workpiece surface. In some embodiments,portions and/or all of the workpiece is heated during exposing.

A new family of etching techniques is ideally suitable for highresolution, high throughput microelectronics manufacturing using aresistless process. This new process family is called digital beamassisted chemical etching (DBACE), and is up to 10 to 100 times moresensitive to ion exposure than milling. The process comprises at leasttwo steps including digital beam exposure of a pattern to the regions tobe etched. The target surface of a workpiece is exposed to very low doseion energy, creating a reactive region for the chemical agent. Theworkpiece is then introduced to reactive gas within a separate chamber.As a result, a high resolution dry chemical etching process activelyremoves the material within the desired location as a parallel processto digital beam pattern exposure on other workpieces within the exposurechamber. As an example, DBACE can be performed on silicon and silicondioxide (SiO₂) with chlorine (Cl₂) or fluorine (F₂) gas, on galliumarsenide (GaAs) with Cl₂, on carbon (e.g., diamond) with oxygen (e.g.,O₂) and nitrous oxide (N₂O₃), on tungsten and molybdenum with carbonbromine trifluoride (CBrF₃) and high temperature superconductors (e.g.,cuprates such as La_(1.85)Ba_(0.15)CuO₄, YBa₂Cu₃O_(7-x) (yttrium bariumcopper oxide, YBCO, Y123, yttrium barium cuprate), andcuprate-perovskite ceramics with or without normal metallic regions)with wet hydroxide chemicals (e.g., sodium hydroxide (NaOH), potassiumhydroxide (KOH)). DBACE has been successfully applied to etch the gaterecesses of gallium arsenide field effect transistor (FET) deviceswithout destroying the underlying active device region.

FIGS. 9A-9C schematically illustrate an example digital beam assistedchemical etching process. In FIG. 9A, an oxide layer 902 has beendeposited over gallium arsenide. In FIG. 9B, the oxide layer 902 isexposed in an exposure chamber 102, for example with gallium ions (Ga⁺),depicted as arrows 904. The workpiece is then transferred to an etchantchamber. In FIG. 9C, a chlorine (Cl₂) etch removes the oxide layer thatwas exposed in the exposure chamber 102, as well as underlying galliumand arsenic as gallium chloride (GaCl₂) and arsenic chloride (AsCl₂),respectively. The result is a trench in the gallium arsenide, asdepicted in FIG. 9C. It will be appreciated that other ion species andetching species may be selected depending on the material or materialsto be etched.

The deposition of thin films has been a staple process inmicroelectronics fabrication. Many techniques have been used to depositthin films, including thermal and electron-beam evaporation, physicalvapor deposition (PVD) (e.g., sputter deposition), chemical vapordeposition (CVD), atomic later deposition (ALD), plating (e.g.,electroplating and electroless plating), and coating (e.g., spincoating). In conventional fabrication, these techniques normally depositmaterial on an entire surface of a workpiece, and the material is formedinto patterns by a liftoff or milling process using a resist patterningprocess. Due to the cost, complexity, and physical limitations of resistpatterning processes, other non-resist techniques are generallypreferred in semiconductor processing. Deposition techniques that mayadvantageously avoid resist patterning processes by exposure to aparticle beam before, during, or after the application of a depositionprocess include particle beam and thermally activated deposition, forexample, but not limited to, digital beam activated CVD, digital beamactivated thermal nucleation, digital beam activated ALD, andchemically-assisted digital beam deposition.

Two examples of direct pattern deposition are ion beam nucleationdeposition (IBND) and chemically assisted ion beam deposition (CAIBD).Both techniques decompose or nucleate atoms on the surface of aworkpiece, but can be limited by slow beam writing techniques. CAIBD isdescribed above with respect to advantages in using a digital beam,although it may be performed without a digital beam. IBND is amulti-PVD/CVD process in which an organic gas is introduced to aworkpiece after it has been exposed by a particle beam. Growth occursfrom the nucleation (exposed) sites similar to ALD. IBND generallyemploys an ion dosage that is about five orders of magnitude less thanCAIBD, which enables IBND to be more than 100,000 times faster thanCAIBD.

In situ deposition processes provide a variety of desired materials forthe fabrication of silicon complementary metal-oxide semiconductors(CMOS), gallium arsenide, and other devices. However, depositionthroughput and film quality are highly desired for such processes. Priorto IBND, reasonable throughput deposition for wafer fabrication was notpossible using in situ beam processing. As an example, the rate of filmdeposition for CAIBD using a large ion dosage (e.g., 4×10¹⁶ ions/cm²)would be limited by the beam current to about 100 A/cm², and it wouldtake over 20 years to deposit one square centimeter for a layer 500 Åthick. IBND, however, is able to produce desired film thicknesses whilealso satisfying throughput and quality concerns. For example, a processresulting in 30% coverage of the usable surface of a 300 mm diameterworkpiece (about 200 cm²) by 2.5 Å of deposited material would takeabout five seconds to expose using an exposure chamber 102 having a beamcurrent density of 10 A/cm², which can expose nucleation sites on theorder of 10 cm²/s. The workpiece can then be transported to a nucleationchamber for deposition while another workpiece is exposed in theexposure chamber 102.

FIGS. 10A-10C schematically illustrate an example digital beam assisteddeposition process. Starting with an unprocessed workpiece in FIG. 10A,portions of the workpiece are exposed with groups of charged particlesof a digital beam, represented by arrows 1002 in FIG. 10B. The workpieceis then transferred to a deposition chamber, where it is exposed toreactant (e.g., a reactant fluid, preferably a reactant gas). Thereactant reacts with the exposed areas to nucleate or atomically deposita material, resulting is the workpiece of FIG. 10C with an area 1104 ofdeposited material.

Integrated microelectronic manufacturing of silicon, gallium arsenide,and other electronics utilize ion implantation to alter device mobilityprofiles at transistor junction edges. Traditional implantationtechniques generally include resist deposition, patterning, development,and baking, followed by ion implantation, resist removal (e.g., byashing and/or stripping), and cleaning. Device fabrication uses a seriesof these implantation techniques, thereby requiring a large number ofpatterning steps. Patterning may be reduced by using serialimplantation, but devices incorporating gradient implantation, lightlydoped drains (LDD), and co-implantation, which can achieve higherperformance, typically trade process simplification for increased deviceperformance. For example, high resolution implantation placementaccuracy may result in increased device reliability and/or processrobustness. Throughput limitations associated with the traditionalimplant techniques are exacerbated by devices that require a largenumber of implantations. Using a conventional CMOS process as anexample, implantation alone (i.e., resist deposition, patterning,development, and baking followed by ion implantation, resist removal,and cleaning) may require about 70 process steps. As a result, the costof the next generation, high leverage electronics can be substantial.

The development of such implantation schemes can be particularly costly.For example, the fabrication of reticle masks used in the resistpatterning steps may take on the order of months and tens of thousandsof dollars. Process development (e.g., the resist exposure conditionsappropriate for the reticle, resist type, resist thickness, etc.) maytake additional months. Once developed, pilot fabrication can take weeksor months. If testing reveals defects in the reticle design or theprocess steps, the process may need to start over, and iterates until afunctional device can be reliably created. Such lengthy development isimpractical or even impossible for certain devices (e.g., specialtymilitary devices where a limited number of devices will be produced).

The use of resistless, direct write implantation can provide themanufacturing flexibility and quick development time to incorporateadvanced techniques (e.g., single-level gradient implantation, LDD, andco-implantation) in research, pilot production, and full productionenvironments. Such a system can achieve vertical implantation profilesranging from about 5 kilo electron volts (keV) to about 500 keV within,for example, about 20 nm. These systems can have the flexibility toselect the species of the ion beam and to place the beam within 9 nm ofitself in a gradient energy or dose profile, which can be used toachieve advanced implantation processes such as gradient implantation,LDD, and co-implantation.

FIGS. 11A through 11D schematically depict a cross-section of aworkpiece processed with direct write implantation. Starting with anunprocessed workpiece in FIG. 11A, the workpiece is implanted with afirst set of digital beam exposure profile, represented by arrows 1100in FIG. 11B. The result is a workpiece of FIG. 11C with an area 1102 ofdoped material. An implantation with a second digital beam exposureprofile, represented by arrows 1104 in FIG. 11C, is then performed. Theresult is a workpiece of FIG. 11D with doped area 1102 and doped areas1106. The workpiece may be annealed after each implantation or after theseries of implantations to activate the dopants. In certain embodiments,the workpiece illustrated in FIG. 11D can be performed with a singleimplantation, for example using the techniques illustrated in FIGS. 11Ethrough 11I.

In FIG. 11E, the charged particle density of the groups of chargedparticles are altered as they are scanned across the workpiece,illustrated by arrow 1108. Area 1110 of the workpiece is lightly doped(e.g., n⁻) while area 1120 is heavily doped (e.g., n⁺⁺). FIG. 11F is aplot of the log of dosage versus position of a workpiece similar to thatof FIG. 11E. The dosage profile can become linear by, for example,overlapping the beams of FIG. 11E. In FIG. 11G, the energy of the beamis altered as it scans across the workpiece, illustrated by arrow 1122.Area 1124 of the workpiece is shallowly doped (e.g., like a lightlydoped drain) while area 1134 is deeply doped (e.g., like an n-well).FIG. 11H is a plot of the implant depth versus position of a workpiecesimilar to that of FIG. 11G. The dosage profile can become linear by,for example, overlapping the beams of FIG. 11G. In some embodiments, theenergy varies between about 5 and 500 keV, or more preferably betweenabout 5 and 200 keV. In FIG. 11I, the charged particle density of thegroups and the energy of the groups are altered as the digital beamscans across the workpiece, illustrated by arrow 1136. Area 1138 of theworkpiece is both lightly and shallowly doped while area 1148 is bothheavily and deeply doped. Although not illustrated, it will beunderstood that other beam parameters, for example species, may also bealtered. In certain embodiments, the beam is altered across atransistor, across a die, or across a workpiece. In certain embodiments,the beam is altered within about a 20 nm area on the workpiece.Alteration of the beam may also enhance etching, deposition, and otherprocesses.

The standard approach for achieving acceptable levels of reliability indevices with gate lengths under 1.5 μm is to incorporate the use of alightly doped drain (LDD) process. This two-step implantation processcreates source and drain regions that lower the electric field near thechannel edge, which lowers the impact ionization rate and results infewer hot carriers available for migration into the gate oxide, therebyenhancing the long term reliability of the device. Beam implantationenables proper horizontal grading of the source/drain implant, whichallows completion of the entire LDD process in a single step. As such,beam implantation can eliminate two photoresist steps and the need for asidewall spacer and its associated etching process, which canparticularly affect yield due to damage to the silicon substrate.

The LDD process can degrade the peak transconductance of a 1 μm gatelength device by roughly 10% and a 0.5 μm gate length device by as muchas 20%. However, elimination of ion implantation on one side can resultin considerable improvements in device performance. With conventionalprocessing, this would require additional patterning steps to mask thesource side, and hence is almost never performed. Beam implantation,however, allows the LDD to be placed only on the drain side of thetransistor channel, where the electric field is high, and ionimplantation can be omitted from the source side. FIGS. 12A through 12Cdepict example schematic cross-sections of implant structures withinworkpieces that can be achieved with a single digital beam process step.

Beam implantation can also be used to improve device scaling. A limitedfactor in controlling device scaling is the source/drain junction depth.The shallower the junction, the fewer the short channel effects and thegreater the degree of scalability. However, a shallow junction resultsin increased parasitic source/drain resistance. The impact of thissource drain/resistance is appreciable for deep sub-micron devices. Thelateral grading potential of beam exposure can be particularly useful inthis instance, for example by making a drain that is very shallow nearthe transistor channel yet deep under the transistor contact. Theshallow junction near the channel edge results in reduced short channeleffects, while the deep junction under the contact promotes low seriesresistance. Another option is placing a deep junction on the source sideand a graded junction on the drain side. This can keep the seriesresistance at a minimum on the source side where it is most importantwhile reducing the negative effect of drain induced barrier lowering onthe drain side.

Lateral channel doping variations produced by digital beam implantationpermit the construction of high performance, high yield planar gateFETs. LDD regions increase the output resistance and breakdown voltageof the transistor, which increases power capability. As illustrated inFIG. 13A, increasing the doping of the source and beneath the gate (area1302 of FIG. 13A) can reduce the source-gate resistance to improve theFET transconductance and gain by increasing the channel current. Thesedesired lateral doping variations, illustrated by the chart of FIG. 13B,can be produced by varying the implant dose in segments along the lengthof the channel. The number of different segments that can be used isonly limited by the digital beam size.

Although GaAs FETs are a key element of many microwave (ormillimeter-wave) monolithic integrated circuits (MIMIC), other elementssuch as Schottky diodes are frequently fabricated on the same workpiecefor high performance devices. However, a FET gate cannot be used as anideal diode because the cutoff frequency is much lower than a highquality Schottky diode. Fabrication of FETs and Schottky diodes on thesame workpiece is difficult to accomplish with either epitaxial growthor blanket implantation processing. Digital beam processing is wellsuited for selective ion implantation processing of FETs and diodes onthe same workpiece because the ability to perform discrete processing atdifferent location on the workpiece, as illustrated in FIG. 15. Theresulting devices are substantially planar, which improves yield. As istrue with all processes described herein, other processing steps may becombined with traditional processes.

GaAs MIMICs are traditionally produced using blanket implantation anddeposition steps, and batch etching and alloying steps. Photoresist isused to selectively mask and define the device and circuit patterns ateach level. Altogether, traditional methods employ over 25 differentprocess steps including 12 mask levels. The front-end (topside) processalone typically takes over 240 hours to complete for a 6-workpiecebatch. The process is very inefficient because of the large amount ofoverhead time and touch labor required. GaAs MIMIC processing can besignificantly improved and simplified to increase yield and lower costby designing a digital beam process of selective pixel basedimplantation, deposition, and etching. Digital beam processing offerstremendous benefits in simplification and improvement of the GaAs MIMICprocess, thereby leading to faster cycle times, higher circuit yields,and lower chip costs. In situ processing can eliminate more than a dozenprocess steps that typically take nearly 100 hours to perform, andenables major process modifications for improving device performance,yield, lowering cost, and expanding capability within an acceptabletimeframe. For example, a digital beam process may comprise only 9 stepsand 19 operations, reducing cycle time to 40 minutes per wafer. Asillustrated in FIG. 16A through 16K, an example GaAs MIMIC digital beamprocess comprises selective channel and contact implants followed byannealing. Ohmic contacts are delineated and contact metal is depositedby digital beam deposition followed by digital beam isolation implant.The contacts are alloyed by annealing. Thin film resistors, FET gates,metal interconnects, insulators, and passivation layers are digital beamdeposited.

Multifunction MIMICS (MFICs) integrate multiple functions in a singledevice. Traditionally, GaAs MFICs have been fabricated with increasedlevels of integration of receiver functions, combining analog anddigital functions, and combining transmitter and receiver functions.MFICs lower system cost by reducing parts count, size, weight, andassembly/tune costs. Wafer scale integration (WSI), which wouldintegrate many dissimilar functions to form a complete system on awafer, is well suited for many generation of future microelectronics.MFICs are generally required for advanced phased array antenna systems,which integrate complex radio frequency functions with optical controland digital signal processing. An example is the System Level IntegratedCircuit (SLIC). Most of the components developed for phased arrayapplications are designed individually using hybrid assembly techniques.Sufficient support functions are not integrated, hence, cannot beinserted into the system directly. Monolithic integration of the circuitfunctions reduces part count, size, weight, and assembly costs.

High electron mobility transistors (HEMT) are heterojunction FETs withgreatly improved performance over conventional GaAs FETs. HEMTs aregenerally used in high speed digital circuits and low noise amplifiersoperating at millimeter-wave frequencies. High speed, ultra-low powerdigital circuits typically have complementary n-channel and p-channelFETs fabricated on the same workpiece, which is difficult, even withselective epitaxial material growth techniques. Digital beam processingimplantation is well suited to fabricate complementary heterojunctioninsulating gate (HIG) FETs on the same wafer. Cross-sections of thebasic n and p channel HIGFET devices are shown in FIGS. 14A and 14B,respectively. The devices are substantially planar and embedded in asemi-insulating substrate. A digital beam comprising silicon can be usedfor the n-channel device implant, and digital beam comprising berylliumcan be used for the p-channel device implant. The metal-silicide gate(e.g., Schottky gate) and ohmic contacts (e.g., comprising AuGe, AuZn)can be deposited by digital beam deposition. Such a sequence allows atwo step in situ device fabrication process. As a result, the uniquefeatures of the device would be a high resolution duel proximityprinting with a minimum step process.

Heterojunction bipolar transistors (HBTs) are typically used in deviceswith high linearity, precision analog, digital/digital converter, andmicrowave power applications. However, current gain and maximumfrequency of oscillation are limited by parasitic base resistance andcollector capacitance, respectively. The performance and yield of GaAsHBT devices can be improved with selective digital beam implantation.FIG. 17 represents an example cross-section of a workpiece under such anapplication. First, beryllium implants into the substrate before contactmetallization reduces contact resistance. The base layer can have alower doping concentration for the same base contact resistance, whichincreases the current gain by promoting electron transportation throughthe p-type base. Second, oxygen or boron implantation between theemitter and base electrodes electrically isolates and confines theelectron current to flow vertically through the device rather thanrecombining laterally. This reduces stray capacitance and improves theoperating frequency. Such fabrication processes are difficult to performwith standard photoresist processing techniques because of the smalldimensions and because photoresist processing increasing surfacerecombination which decreases gain.

The lateral doping capability of a beam implant can also improve devicescalability through use of channel stop implants. Such channel stopimplants usually reduce the effective device width of narrowtransistors, reducing the junction capacitance and increasing theperformance of the technology. With conventional implants, difficulty intailoring the doping concentration along the edge of the field oxide canresult in more implant than needed going into the active area. With abeam exposure, the implant can be spatially controlled to keep asufficient, but not excessive, surface concentration along the fieldoxide edge.

Varying the channel stop implant can include grading a channel stop orguard ring implant along a bird's beak to prevent field inversionresulting from ionizing radiation. Guard ring approaches normally resultin large area penalties because the implant dose required for hardnessis sufficiently high to promote breakdown problems from the closeproximity of n⁺/p⁺ regions. Leaving a space between the guard ring andthe n⁺ implant layers can solve this breakdown problem (e.g., asdepicted in FIG. 19A). Although effective, this approach can result in alarge density penalty, especially as devices are scaled into thesub-micron regime. Using a digital beam exposure, a horizontal dopinggradient can decrease the ion dosage near the junction edge, where thefield oxide is thin and thus less sensitive to radiation, and canincrease the ion dosage under the thicker part of the field oxide. Usingsuch a strategy can achieve excellent radiation hardness, while notcompromising the layout density due to the potential breakdown problem.Implantation of a non-conducting layer can be used to form a very denseisolation approach. An implantation of sufficient dosage (e.g., betweenabout 1×10¹⁵ charged particles/cm² and 1×10¹⁷ charged particles/cm²)forms amorphous regions with essentially infinite resistivity (e.g., asdepicted in FIG. 19B). Devices can thus be isolated from each other bythis high resistance region. The dimensions of this isolation region canbe extremely small, for example much smaller than an oxide isolationguard ring, resulting in greatly improved circuit densities.

In some CMOS applications, the use of a bipolar transistor can be verydesirable. This has led to the widespread interest in BiCMOS technology.Many of these applications do not require a high frequency bipolardevice, and hence the greatly increased process complexity associatedwith BiCMOS is not warranted. A lateral bipolar device exists in everyCMOS technology, but typically performance is too poor to havewidespread use. Using beam exposure implantation can greatly improve theperformance of this lateral bipolar transistor technology. Horizontalgrading in the channel (base) region can result in electric field aidedminority carrier transport, improving both transistor beta andtransition frequency (F_(t)). An LDD process destroys the emitterefficiency of this bipolar device, so the ability to selectively placeLDDs on the drain side of the channel allows the source regions to actas emitters and to not be processed as LDDs.

It will be appreciated that digital beam implantation can be used forother applications and devices, and the embodiments described herein areonly examples. It will also be appreciated that combinations of digitalbeam processes including etch, implant, and deposition can be used toform a wide variety of semiconductor devices and the embodimentsdescribed herein are only examples. For example, FIG. 18 depicts aprocess sequence for building a substantially completed semiconductordevice. Some steps may be performed with traditional methods andcombined with digital beam processing, or, preferably, each of theprocess steps is performed using digital beam processing.

Annealing is a process by which the atoms or molecules in a materiallayer are heated or energized in order to activate dopants, changefilm-to-film or film-to-wafer substrate interfaces, densify depositedfilms, change states of grown films, repair damage from ionimplantation, move dopants, drive dopants from one film into another orfrom a film into the wafer substrate, to drive off excess solvents(e.g., from resist deposition, spin-on dielectrics, etc.), and the like.As such, annealing is particularly useful in conjunction with directwrite processes. However, it will be appreciated that a workpiece neednot be exposed in a beam exposure chamber prior to rapid thermalannealing.

Combinations of the above and other processes can be used to produceworkpieces that are substantially finished (e.g., ready for passivation,ready for die cutting, etc.) from a bare substrate (e.g., asingle-crystal wafer, a workpiece with a deposited field oxide) in asingle processing tool.

The demand for military and commercial electronics will continuallydrive advances in a wide range of integrated circuits that use the sameor similar forms of logic cells. Over the past several years, multipleexposure technologies have been used to meet the demands of the everdecreasing next node critical geometries. Generally, increasing thenumber of processing steps reduces manufacturing yield and throughput,resulting in expediential cost increases per new design rule. Apromising manufacturing technology, which simultaneously addresses cost,resolution, and throughput and process yield improvement does notcurrently exist for the future development of new devices. A paradigmcombining semiconductor processing and lithography to offer digital beampattern processing can thus provide a solution to the future of theindustry.

Incorporating resistless digital beam exposure aided deposition,etching, and implantation processing on a fully automated, highthroughput cluster processing tool can provide a significant reductionin the manufacturing cost of high performance and/or high densityintegrated circuits. For example, the manufacture of a partially in situ15 nm source/drain BiCMOS device can include the spontaneous nucleationof tungsten, silicon oxide, and platinum for the alignment ormetallization, dielectric insulators, and silicide, respectively. A deepsub-micron polysilicon gradient implantation source/drain technology canbe used to minimize the number of implantation levels while maximizingthe performance of the devices. DBACE can be used for LOCOS and theformation of gate oxides. Polysilicon for the implantation, gate, andpassivation levels can be deposited on the entire wafer in a CVD chamberon the apparatus. The field oxide can be the only ex situ process doneoutside of the system prior to all other processes.

Several different pixel/digital beam spot size combinations can be usedfor exposure at different workpiece levels in order to simultaneouslymaximize the resolution and throughput of the processing tool. Exposurestrategies can also be used to compensate for uniform nucleationdeposition as discussed above. To increase the sensitivity of thedigital beam exposure aided deposition process, several levels can beexposed with reduced beam current density without reducing thethroughput of the system. In order to perform a complete in situprocess, the tool can include one or more dedicated oxidation (e.g.,plasma enhanced CVD (PECVD)) and nucleation chambers.

Masks

As described above with respect to FIGS. 9A-9C, a workpiece may beexposed with groups of charged particles and then transferred to anetchant chamber. In the etchant chamber, a reactant gas removes theportions of the workpiece exposed to the charged particles. Othermethods of processing a workpiece use conformal masks. Conformal maskprocessing techniques can improve the throughput of the focused ion beamsystem. Example processes for forming light field and/or dark fieldconformal masks are described below. These conformal masks can beincorporated into other fabrication processes. For example, a conformalmask could serve as a process mask for subsequent deposition,implanting, or etching of semiconductor materials.

Ion beam processing of semiconductor (or other) devices is an attractivealternative to exposure of photoresist by light. The advantage ofdefining patterns with ions instead of photons is particularly apparentas pattern feature sizes become smaller than the photon wavelengths. Theresolution of photolithography processes based on optically imaging areticle onto a workpiece such as a semiconductor wafer are restricted byseveral factors including the diffraction limit, which depends on thewavelength of light. Accordingly, photolithography systems that utilizelight of shorter and shorter wavelengths are being developed to increasethe resolution and reduce the critical dimension. Light sources in thex-ray and shorter wavelengths, however, have further thermal transfercomplications relating to pattern overlay inaccuracies and are difficultto produce and project. Ion beams, in contrast, can be produced,accelerated, and used to create patterns with minimal thermal transferand non-linear pattern overlay correction by a number of methods, forexample by direct writing or by projection through physical masks. Amajor limitation, however, of ion beam lithography is the slowdeflection speed causing a relatively long time required to write finelines on workpieces using equipment that is also typically expensive.Processes such as ion beam etching and deposition may involve higher iondoses and consequently may further decrease throughput. Hence, it isdesirable to produce patterns in a mask material using decreased ionbeam doses. The patterns can be subsequently processed outside the ionbeam chamber to transfer the pattern to a process mask, after which theworkpiece may be etched, deposited upon, or ion implanted using othermethods and apparatuses.

A conformal mask may be formed from a stack of layers. In a preferredembodiment, each layer has a high etch selectivity and is thinner thanthe layer below it. The topmost layer preferably has a thickness on thescale of angstroms, which decreases the exposure time required for ionbeam sputtering. Reducing the thickness of the topmost layer operated onby the ion beam reduces the amount of ions necessary to pattern the toplayer, for example, to write a pattern in the topmost layer. Hence, thedose and/or time of exposure of the ion beam is reduced. The ratio ofatoms removed per exposing pixel area can also be adjusted bycontrolling the beam parameters (ion species, beam energy, and beamcurrent). Selecting the specific materials for binding energy andchemical interaction with the ion beam parameters for the purpose ofobtaining a high sputter yield (atoms per ion removed) can improvethroughput of the process. A high sputter yield reduces the ion doseand, hence, exposure time thus improving exposure throughput.

Once the topmost layer has been patterned by the ion beam and theexposed areas are removed, the substrate may be processed to removematerial in a lower layer, thereby transferring patterns in the toplayer down to the lower layer or layers. The substrate, for example, maybe processed in a Reactive Ion Etch (RIE) or other etch chamber. RIE ispreferable for its high selectivity and anisotropy, however other etchprocesses can be used. Wet etch may be suitable in some embodiments.Other dry etches, such as ICP, Plasma enhanced ECR, or Ion Mill may alsobe substituted for Reactive Ion Etch to achieve the same effect. In someembodiments comprising a photosensitive layer, exposure to light or UVand developer can be used to remove mask material from thephotosensitive layer and transfer the patterns.

Alternating etches with appropriate ion species can be used toselectively etch through the layers, transferring the pattern down fromthe topmost layer to a bottom layer, e.g., an organic layer, which canact as a mask for subsequent processing. Selective etching refers toetching processes in which one material is etched rapidly while theother is etched very slowly or not etched at all. The cascading oflayers of increasing thickness combined with pattern transfer processeswith high selectivity can enable a thin top mask layer configured forion beam writing to define a thicker process mask layer, where therelative thickness increase is the product of the selectivity ofsubsequent layer etches.

Example processes for producing both light field and dark fieldconformal masks are disclosed. In certain embodiments, the pattern isdefined in a very thin topmost layer, advantageously providing highresolution while high energy ions do not impact the semiconductorsurface, thereby avoiding unintentional damage to the underlyingdevices.

A bare or in-process semiconductor wafer (or other substrate orworkpiece), which may have various patterned layers or devices on itssurface, is coated with a process mask layer that resists subsequenttraditional process steps in the device fabrication, for example, butnot limited to, wet or dry etching, deposition of conductor,semiconductor, or insulator, and ion implantation. In certainembodiments, the process mask layer is organic. Photoresist is a goodexample of a suitable organic, although its light sensitive propertiesare not required in all embodiments. Integration with organic processmasks such as photoresists offers a variety of advantages. Organic masksare preferred in certain embodiments for their resistance to chemicals.The use of an organic process mask layer beneath the FIB mask layer mayalso ensure that ion damage does not penetrate to and thereby damagesemiconductor devices below the mask.

In certain embodiments, an etch mask layer is deposited. The etch masklayer material can be selected, for example, to be etched by a reactiveion etch that does not etch organic material. Suitable etch mask layermaterials are materials such as metalloids or semiconductors such assilicon (Si) or metals such as titanium (Ti). Other materials, however,may be used. In various embodiments, the etch mask layer is thinner thanthe process mask layer. Such materials can be deposited, for example, bythermal or e-beam evaporation or sputtering. Many plasmas can also beused for depositions; these typically uniformly deposited films canadvantageously be easily removed using solvents which dissolve theorganic process mask utilized in some embodiments.

Next, a FIB mask layer comprising a material that can be efficientlyremoved by a FIB is deposited. In certain embodiments, the FIB masklayer material is selected to provide high etch selectivity to theetching of the etch mask layer. The FIB mask layer can also be selectedto provide etch selectivity to the etching of the process mask layer. Invarious embodiments, the FIB mask layer is thinner than the etch masklayer and/or the process mask layer.

In the example embodiment illustrated in FIG. 22A, an in-processpatterned silicon substrate 2210 is first coated with a process masklayer 2220. The process mask can be, for example, between 1 and 1000 nmthick (e.g., comprising between about 100 and 300 nm of an organicmaterial). In embodiments in which the process mask layer 2220 comprisesan organic material, a standard spin and bake method may be employed. Anetch mask layer 2230 (e.g., comprising about 10 nm of Si or Ti) isdeposited on the process mask layer 2220. Example deposition processesfor the etch mask layer 2230 include sputtering and e-beam evaporation.A FIB mask layer 2240 (e.g., about 1-2 nm thick) is deposited on theetch mask layer 2230. In some embodiments, the FIB mask layer 2240comprises an oxide layer (e.g., silicon dioxide (SiO₂) or aluminum oxide(Al₂O₃)), for example, deposited by sputtering or evaporation.

The wafer is then transferred into a FIB chamber. Upon registration ofalignment marks, a FIB 2250 writes a desired pattern on the surface withthe appropriate ion type, energy, and dose to remove certain portions ofthe FIB mask 2240, as shown in FIG. 22B. Any suitable FIB write processand/or chamber may be used. As described above, in certain embodiments,a stream of charged particles emanates from a charged particle sourceand is collimated and directed along an axis. The physical properties ofthe beam of charged particles traveling along the axis with adistribution transverse to the axis can be modified to provide a highspeed, digital (or “pulsed”) distributed writing beam. Various methodscan be used to create a wave of temporally and spatially definedhigh-density charged particle anti-nodes and low density (or no density)nodes, traveling in a longitudinal path of accelerated particles (a“digitized beam”). As further described above, certain FIB exposurechambers are able to write only where written features are to be formedbecause the digital beam only scans selected areas, but the beam doesnot need to be turned off to be moved to another area. In certainpreferred embodiments (e.g., using the FIB chamber described above), theFIB chamber can adjust ion type, energy, dose, position, etc. Forexample, writing with a digital beam can preferably augment transformedpattern data to compensate for deflection field distortion, waferdistorted pattern placement errors, stage position, etc. The FIB maskthickness is very thin in some embodiments, as it only has to withstandthe transfer of the pattern to the etch mask. In these embodiments, theFIB beam spot is reduced, thus avoiding the backscattering bloom thattypically occurs as the beam penetrates further into the mask material.

In alternative embodiments, the FIB system is coupled (e.g., fluidlycoupled under vacuum) to an atomic layer deposition (ALD) system. ALDdeposits monolayer coverage of oxides by a first exposure of the wafersurface to a precursor gas that adsorbs on the surface and then a secondexposure to a reactive gas that combines with the adsorbed precursor toproduce a monolayer of oxide. By repeated exposure to the two gascycles, oxide layers can be grown with monolayer control and excellentconformal coverage. In such embodiments, the wafer with the process maskor process and etch mask is first exposed to the precursor. As shown inFIG. 22B, the precursor can be easily removed by subsequent exposure toFIB as it is an adsorbed molecule and not yet an oxide, advantageouslyimproving ion sputter yield and reducing the requisite ion dose. In thismanner, the FIB can pattern the precursor. In such embodiments, thewafer is finally exposed to the reactive gas to complete the cycle,providing monolayer coverage of oxide that has been patterned by theFIB.

Once the FIB mask layer 2240 is patterned, the pattern is transferred toa lower layer. The wafer, for example, may be etched using a dry etchsuch as a reactive ion etch (RIE) process. RIE (e.g., as shown in FIG.22C) can etch the exposed portions of a lower layer across the entirewafer. In certain embodiments, the pattern transfer process isconfigured to improve the etch selectivity to one layer relative toanother layer (or other layers). For example, the selectivity of an RIEprocess to the etch mask material 2230 relative to the FIB mask material2240 can be around 100×. That is, the etching rate of the etch masklayer 2230 is 100 times faster than that of the FIB mask layer 2240using the RIE process in that embodiment. In certain embodiments,chlorine RIE can be used to etch the Si or Ti etch mask material.Chlorine may be selected because it does not typically react with theoxide in the FIB mask layer 2240 or organic material in the process masklayer 2220, while it is generally highly reactive with Ti and Si. Thepattern in the FIB mask layer 2240 is thus transferred to the etch masklayer 2230 or, in certain embodiments, to the process mask layer 2220.

Such processes may advantageously retain the critical dimensions ofcertain features in a thicker lower layer, for example, an etch masklayer 2230 that is thicker than the FIB mask layer 2240. Moreover,because the FIB mask layer 2240 is patterned without a reticle, thepattern can adjust for nonconformities on the wafer.

In embodiments comprising an etch mask layer, the pattern maysubsequently be transferred to the process mask layer 2220, for example,etched using a suitable RIE that preferably does not react with the etchmask layer 2230. The anisotropic nature of the RIE again allows thecritical feature dimensions to be maintained while the pattern istransferred to the thicker material of the process mask layer 2220. Inthe embodiment illustrated in FIG. 22D, an oxygen RIE having a beam 2270of reactive ions etches the process mask layer 2220, while it does notsubstantially react with the either Si or Ti of the etch mask layer2230. In certain embodiments, the FIB mask layer 2240 is removed by oneof the processes for transferring the pattern through the variouslayers; for example, the FIB mask layer may be sputtered away duringoxygen RIE as a result of being thin. The FIB mask layer 2240 may alsointentionally be removed by another separate process.

Other pattern transfer processes can be used. For example, in certainembodiments comprising a photosensitive process mask layer, the wafer asillustrated in FIG. 22C is exposed to an appropriate wavelength and theexposed portions of the process mask layer 2220 are developed away(e.g., using a wet chemical develop). The etch mask layer 2230 shieldsthe unexposed portions such that a traditional reticle is not needed.Such embodiments allow integration with existing fabrication equipment.However, wet chemical developing may in some embodiments increase thecritical dimensions of certain features.

FIG. 22D shows the resultant conformal mask (layers 2220, 2230). Thewafer is ready for subsequent processing using this conformal mask.

In various embodiments, it may be undesirable to leave the etch masklayer 2230 on the process mask layer 2220 during a process mask etch. Inthese embodiments, the process for transferring the pattern through theprocess mask layer can be stopped prematurely. For example, the oxygenRIE can be stopped before the process mask layer 2220 has beencompletely etched through, for example at about 70% completion, to allowfor variations in the layer and etch across the wafer. A suitablechemical process for removing the etch mask layer, for example a carbontetrafluoride (CF₄) or chlorine plasma etch, can optionally be used tostrip the patterned etch mask layer 2230. The wafer can then be returnedto the oxygen RIE or other suitable etch, and the entire process masklayer 2220 is thinned (or “etched back”) while the pattern istransferred to the wafer surface (e.g., in the form of trenches).

Such processes may result in what can be referred to as a “dark fieldmask,” where the areas that are exposed to the FIB become openings inthe process mask layer 2220. In certain embodiments, reducing orminimizing the area exposed in the FIB chamber can increase thethroughput of the FIB chamber. Depending on the pattern and subsequentprocess step, dark field or light field patterns are preferred. The useof both process types can ensure that exposure desirably does not exceed50% of the wafer surface in certain embodiments.

The preparation of an example light field conformal mask is illustratedin FIGS. 23A-23F. A first process mask layer 2320 (e.g., similar to theprocess mask layer 2220 described above), such as an organic material,is deposited over a wafer substrate 2310. A plating base layer 2324 canbe deposited over the first process mask layer 2320. In certainembodiments, the plating base layer 2324 comprises a metal. Manydifferent metals can be selected for the plating base layer 2324depending on what would be appropriate for subsequent process steps. Incertain embodiments, for example, the plating base layer 2324 comprisesa conductive metal such as titanium. A second process mask layer 2326,e.g., a second organic mask layer, is deposited. The embodiment shown inFIGS. 23B-23D is similar to the pattern transfer sequence describedabove for FIGS. 22B-22D, but the pattern is transferred down to theplating base layer 2324 rather than down to the substrate 2310 (e.g.,including transferring the pattern to the second organic layer 2326using either RIE beams 2360, 2370 or non-reticle exposure). In certainembodiments, the FIB mask layer 2340 is removed by one of the processesfor transferring the pattern through the various layers; for example,the FIB mask layer may be sputtered away during RIE as a result of beingthin. The FIB mask layer 2240 may also intentionally be removed byanother separate process.

In an embodiment illustrated in FIG. 23E, the wafer is transferred to anapparatus that fills the opening in the second process mask layer tocreate a fill layer. In certain embodiments, this can be accomplishedusing an electroplating apparatus. Selective electroplating using theplating base 2324 for cathodic electrical contact fills the opening inthe second organic layer 2326 with an electroplated material 2380,thereby producing a metal mask 2390 while maintaining the criticaldimensions of the pattern features. Other embodiments may comprise anelectroless plate to create the fill layer. Other kinds of chemicalreactions that could convert the chemistry of the exposed surface,changing the etch selectivity, may also be suitable alternativeembodiments to a fill layer. Many different materials can be selectedfor the fill layer 2390, for example metals, depending on desiredproperties and what would be appropriate for subsequent process steps.In some embodiments, plating techniques such as pulsed plating can beused to ensure uniform electroplating across the wafer. Other processes,however, can be used in different embodiments.

The wafer may then be transferred to an etch or other suitable chamber,for example, an RIE chamber, where the pattern in the fill layer 2390 istransferred through the process mask layer 2320, for example as shown inthe embodiment of FIG. 23F. Beams 2394 of alternating RIE ions or othersuitable process can be used to remove mask materials such as 2330,2326, 2324, 2320 while the materials 2324, 2320 under the fill layer2390 are not removed. For example, chlorine RIE can be used to etch theetch mask layer 2330, oxygen RIE can be used to etch the second processmask layer 2326, chlorine RIE can be used to etch the plating base layer2324, and oxygen RIE can be used to etch the first process mask layer2320. Such a sequence can produce a light field pattern where the firstprocess mask layer 2320 is protecting the areas where the FIB mask layer2340 was exposed to the FIB beam 2350. In some embodiments, the filllayer 2390 comprises electroplated lines which are the finished finalproduct to be incorporated into the wafer.

FIG. 23F shows the resultant conformal mask (layers 2390, 2324, 2320).The wafer is ready for subsequent processing using this conformal mask.In certain embodiments, a light field conformal mask can be createdusing focused ion beam deposition. As described above, FIB can be usedto deposit a thin patterned top layer, preferably on 50% or less of awafer surface. The wafer can be subsequently processed using the patterntransfer sequence described above for FIGS. 22C-22D.

In certain embodiments, the above processes for producing dark field andlight field conformal mask patterns on workpieces advantageously allowsintegration of FIB patterning with a wide range of semiconductor orother fabrication processes that otherwise are integrated withlight-patterned photoresist. These and other embodiments enable FIBdirect pattern (resistless) processing described above to conform tomany semiconductor processing and other fabrication methods byintegrating the use of a process mask, e.g., resist. These processes mayalso enable the use of a very thin FIB mask layer that needs reduced orminimal FIB exposure while producing a relatively thick process masklayer having critical dimensions of the features patterned in the FIBmask layer. Using the FIB to remove the thin surface pattern instead ofexposing resist to light radiated through a reticle provides improvedcritical dimension and fidelity that is desirable for ever-decreasingsemiconductor features sizes.

A wide variety of variations are possible. Components may be added,removed, or reordered. Different components may be substituted out. Thearrangement and configuration may be different. Similarly, processingsteps may be added or removed, or reordered.

Applications for this technology are virtually unlimited and span farbeyond the development of tomorrow's microelectronics components.Described above are a small number of high leverage electronicsapplications to demonstrate the potential of resistless processing, forexample in the military and commercial electronics industries. A widevariety of other applications are possible. It will be appreciated thatthe majority of the in situ process steps can include a reduction in thesystem beam current density to 40 A/cm². This is equivalent to presentday technology and greatly reduces the risk for each of these tasks.

Although this invention has been disclosed in the context of certainpreferred embodiments and examples, it will be understood by thoseskilled in the art that the present invention extends beyond thespecifically disclosed embodiments to other alternative embodimentsand/or uses of the invention and obvious modifications and equivalentsthereof. In addition, while several variations of the invention havebeen shown and described in detail, other modifications, which arewithin the scope of this invention, will be readily apparent to those ofskill in the art based upon this disclosure. It is also contemplatedthat various combinations or sub-combinations of the specific featuresand aspects of the embodiments may be made and still fall within thescope of the invention. It should be understood that various featuresand aspects of the disclosed embodiments can be combined with, orsubstituted for, one another in order to form varying modes of thedisclosed invention. Thus, it is intended that the scope of the presentinvention herein disclosed should not be limited by the particulardisclosed embodiments described above or below.

1. A method for processing comprising: providing a workpiece comprisinga particle beam patternable layer that is configured to be first removedthrough interaction with a particle beam and a transfer layerthereunder; and exposing regions of the particle beam patternable layerusing a focused particle beam thereby removing said regions; wherein thefirst transfer layer is configured to be selectively processed relativeto the particle beam patternable layer; and removing the transfer layerusing a second removal process which selectively removes regions of thetransfer layer, wherein a shape of the second removal is substantiallydetermined by a shape created by the regions removed by an earlierexposure.
 2. The method of claim 1, wherein the first exposing step isachieved through ion milling, sputtering the particle beam, chemicallyassisted etching by the particle beam, or reactive ion etching of theparticle beam patterned layer.
 3. The method of claim 2, wherein saidfirst transfer layer is between said particle beam patternable layer andsaid second transfer layer.
 4. The method of claim 2, wherein the firsttransfer layer is configured to be selectively processed relative to thesecond transfer layer using said first removal process.
 5. The method ofclaim 2, wherein the second transfer layer thickness is between 75% and50% of the minimum patternable feature size width.
 6. The method ofclaim 2, wherein the first transfer layer is a conductive material. 7.The method of claim 2, wherein the first transfer layer is deposited byatomic layer deposition full cycle.
 8. The method of claim 2, whereinthe first transfer layer is deposited by atomic layer deposition halfcycle.
 9. The method of claim 2, wherein the first transfer layer isdeposited by atomic layer deposition multiple cycle.
 10. The method ofclaim 2, wherein the first transfer layer is Aluminum.
 11. The method ofclaim 2, wherein the first transfer layer is Aluminum composite.
 12. Themethod of claim 2, wherein the first transfer layer comprises aconductively doped semiconductor or metalloid.
 13. The method of claim10, wherein the first transfer layer comprises conductively dopedsilicon.
 14. The method of claim 10, wherein the first transfer layercomprises conductively photo resist.